Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1995-02-23
1997-05-13
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257763, 257766, H01L 2348
Patent
active
056295642
ABSTRACT:
A structure for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.
REFERENCES:
patent: 3633076 (1972-01-01), Arnot et al.
patent: 4290079 (1981-09-01), Carpenter et al.
patent: 4434434 (1984-02-01), Bhattacharya et al.
patent: 4840302 (1989-06-01), Gardner et al.
patent: 4954870 (1990-09-01), Takemura et al.
patent: 4985750 (1991-01-01), Hoshino
patent: 5162257 (1992-11-01), Yung
patent: 5268072 (1993-12-01), Agarwala et al.
R. J. Herdzik, et al., Barrier Layer Metallurgy for Aluminum Stripes, IBM Technical Disclosure Bulletin, V. 10, No. 12, p. 1979, May 1968.
P. A. Totta, et al., SLT Device Metallurgy and Its Monolithic Extension, IBM Jrl. of Research & Development, V. 13, No. 3, pp. 226-238, May 1969.
B. S. Berry, et al., Studies of the SLT Chip Terminal Metallurgy, IBM Jrl. of Research & Development, May 1969.
R. A. Leonard, et al., Chromium Barrier for Terminal Metallurgies,, IBM Technical Disclosure Bulletin, V. 13, No. 5, p. 1121, Oct. 1970.
H. M. Dalal, et al., Chromium-Copper Step-Phasing, IBM Technical Disclosure Bulletin, V. 20, No. 3, pp. 1005-1006, Aug. 1977.
T. Kawanobe, et al., Solder Bump Fabrication By Electrochemical Method for Flip Chip Interconnection, IEEE CH1671, pp. 149-155, 1981.
M. Warrier, Reliability Improvements in Solder Bump Processing for Flip Chips, IEEE 0569-5503, pp. 460-469, 1990.
Nye, III Henry A.
Roeder Jeffrey F.
Tong Ho-Ming
Totta Paul A.
Crane Sara W.
International Business Machines - Corporation
Potter Roy
Srikrishnan Kris V.
LandOfFree
Electroplated solder terminal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electroplated solder terminal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electroplated solder terminal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1387493