Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-08-27
2003-01-28
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189020
Reexamination Certificate
active
06512713
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an electronic, current-sensitive amplifier circuit for amplifying electrical current, which is supplied from a row or a column of a matrix array of electronic or optoelectronic components. The matrix array is formed therein in particular by a cell field composed of memory cells, in particular static SRAM memory cells. However it can also be defined by a cell field of photodetectors, in particular photodiodes. The invention also relates to such a matrix array of memory cells, in particular static SRAM memory cells or photodetectors, especially photodiodes. The matrix array is connected to an amplifier circuit according to the invention which itself is coupled to a multiplexer circuit that drives the amplifier circuit.
Electronic amplifier circuits for reading out memory cell fields, which are referred to as current sense amplifiers, according to the principle of current detection have a shorter readout delay in comparison with voltage detection because the current of the memory cell is extracted with low impedance. That has been described in particular in the publications entitled “Current-Mode Techniques For High-Speed VLSI Circuits With Application to Current Sense Amplifier For CMOS SRAMs” by Seevinck et al. in IEEE Journal of Solid-State Circuits, vol. 26, No. 4, pages 525-536 (referred to below as “Seevinck”) and “Current Sense Amplifiers For Low-Voltage Memories” by N. Shibata in IEICE Trans. Electron., Vol. E79-C, No. 8, pages 1120-1130 (referred to below as “Shibata I”). The smaller the input resistance of the current sense amplifier, the shorter the time required to read out the memory contents.
The invention relates in particular to memory architectures in which each current sense amplifier is assigned a plurality of columns (bit line pairs), one of which is connected to the current sense amplifier by a multiplexer circuit in each case. Such a configuration is illustrated in FIG.
1
and discussed in greater detail below. However, a MOS transistor which is respectively selected and switched on by a multiplexer circuit has a finite resistance that is located in series with an input resistance of a current sense amplifier and thus has a disadvantageous influence on the timing behavior and the level of the signal current flowing into the current sense amplifier. That has been investigated in a publication entitled “Megabit-Class Size-Configurable 250 MHz SRAM Macrocells With a Squashed Memory Cell Architecture” by N. Shibata et al., in IEICE Trans. Electron., Vol. E82 C, No. 1, pages 94-103 (referred to below as “Shibata II”).
In the prior art, such disadvantages are usually accepted, as is shown by a publication entitled “A 7-ns 140 mW 1-Mb CMOS SRAM With Current Sense Amplifier” by K. Sasaki et al. in IEEE Journal of solid-state circuits, Vol. 27, No. 11, pages 1511-1518 (referred to below as “Sasaki”).
Alternatively, current sense amplifiers with the classic principle of voltage detection are used to read out static memory cells (“Seevinck”, FIG.
10
). In that case, the bit line voltage is tapped with high impedance. Since there is virtually no current flowing across the multiplexer transistor, its resistance is uncritical with respect to the timing period. However, in principle the voltage detection is slower than the current detection because the high bit line capacitance has to be recharged.
As a further alternative solution to the above-mentioned problems, current sense amplifiers with such a small surface that they can be assigned precisely to one bit line pair (“Seevinck”) are used. The multiplexer disposed at the point which is critical for the readout time, between the bit line and the current sense amplifier, is thus dispensed with.
However, the increased number of current sense amplifiers leads to an increased space requirement.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an electronic amplifier circuit having a switchable input transistor, a matrix array of memory cells and a matrix array of photodetectors, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which the electronic amplifier circuit is current-sensitive and has improved properties, in particular improved timing behavior for amplifying current from a matrix array of electronic or optoelectronic components.
With the foregoing and other objects in view there is provided, in accordance with the invention, in a memory configuration having a matrix array of electronic or optoelectronic components in rows or columns, and a multiplexer circuit supplying a control signal, an electronic, current-sensitive amplifier circuit for amplifying electrical current from the rows or columns. The amplifier circuit comprising input transistors to be driven and switched by the control signal. The input transistors are each connected to a respective one of the rows or columns.
The input transistor of the interface circuit is thus used simultaneously as a switching transistor of the multiplexer circuit. Instead of a fixed voltage, the gate terminal of the input transistor is driven by the multiplexer signal. In that way, the transistor can be switched on and off and itself becomes functionally part of the multiplexer circuit. In the switched-on state (gate terminal connected to the operating voltage or to ground depending on the type of transistor), the transistor acts as an amplifier according to the principle of the gate circuit (cascode) and produces the required low input resistance. Current sense amplifiers according to that principle implement the simplest form of current detection, but have a relatively high input resistance in comparison with more complex circuits (“Shibata I”, Table 1). However, the proposed combination with the multiplexer function provides an advantage in terms of area over other solutions. The solution according to the invention is thus highly suitable for products with severe restrictions in terms of spatial requirements and average requirements in readout speed. Since no additional amplifiers are required, the power consumption is also not very high. The circuits according to the invention are also highly reliable due to their simplicity.
The invention is suitable in particular for a memory cell array, especially a cell field, made of static SRAM memory cells. However, the amplifier circuit according to the invention can also be coupled to a matrix of photodetectors, in particular photodiodes, having pixels which can also be connected through a multiplexer to a current sense amplifier. The advantages of the amplifier circuit according to the invention are also applicable in this case.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
The invention is illustrated and described herein as embodied in an electronic amplifier circuit having a switchable input transistor, a matrix array of memory cells and a matrix array of photodetectors.
The invention is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Seevinck, Evert et al.: “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's”, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, dated
Paul Steffen
Wicht Bernhard
Greenberg Laurence A.
Locher Ralph E.
Stemer Werner H.
Tran M.
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