Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-03-30
2002-07-30
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C710S068000, C710S022000, C345S519000, C711S147000
Reexamination Certificate
active
06427194
ABSTRACT:
The present application contains some text and drawings in common with U.S. patent application Ser. No. 08/702,911, filed Aug. 26, 1996, and issued Sep. 22, 1998 as U.S. Pat. No. 5,812,789, entitled: “VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION DEVICE THAT SHARES A MEMORY INTERFACE” by Raul Z. Diaz and Jefferson E. Owen, which had the same effective filing date and ownership as the present application, and to that extent is related to the present application, which is incorporated herein by reference.
BACKGROUND
The present invention relates to the field of electronic systems having a video and/or audio decompression and/or compression device, and is more specifically directed to sharing a memory interface between a video and/or audio decompression and/or compression device and another device contained in the electronic system.
The size of a digital representation of uncompressed video images is dependent on the resolution and color depth of the image. A movie composed of a sequence of such images, and the audio signals that go along with them, quickly become large enough so that, uncompressed, such a movie typically cannot fit entirely onto a conventional recording medium such as a Compact Disc (CD). It is now also typically prohibitively expensive to transmit such a movie uncompressed.
It is therefore advantageous to compress video and audio sequences before they are transmitted or stored. A great deal of effort is being expended to develop systems to compress these sequences. Several coding standards currently in use are based on the discrete cosine transfer algorithm including MPEG-1, MPEG-2, H.261, and H.263. (MPEG stands for “Motion Picture Expert Group”, a committee of the International Organization for Standardization, also known as the International Standards Organization, or ISO.) The MPEG-1, MPEG-2, H.261, and H.263 standards are decompression protocols that describe how an encoded bitstream is to be decoded. The encoding can be done in any manner, as long as the resulting bitstream complies with the standard.
Video and/or audio compression devices (hereinafter “encoders”) are used to encode the video and/or audio sequence before it is transmitted or stored. The resulting bitstream is decoded by a video and/or audio decompression device (hereinafter “decoder”) before the video and/or audio sequence is displayed. However, a bitstream can only be decoded by a decoder if it complies with the standard used by the decoder. To be able to decode the bitstream on a large number of systems, it is advantageous to encode the video and/or audio sequences in compliance with a well accepted decompression standard. The MPEG standards are currently well accepted standards for one-way communication. H-261, and H.263 are currently well accepted standards for video telephony.
Once decoded, the images can be displayed on an electronic system dedicated to displaying video and audio, such as television or a Digital Video Disk (DVD) player, or on electronic systems where image display is just one feature of the system, such as a computer. A decoder needs to be added to these systems to allow them to display compressed sequences, such as received images and associated audio, or ones taken from a storage device. An encoder needs to be added to allow the system to compress video and/or audio sequences, to be transmitted or stored. Both need to be added for two-way communication such as video telephony.
A typical decoder, such as an MPEG decoder
10
shown in
FIG. 1
a
, contains video decoding circuit
12
, audio decoding circuit
14
, a microcontroller
16
, and a memory interface
18
. The decoder can also contain other circuitry depending on the electronic system in which the decoder is designed to operate. For example, when the decoder is designed to operate in a typical television, it will also contain an on-screen display (OSD) circuit.
FIG. 1
b
shows a better decoder architecture, used in the STi3520 and STi3520A MPEG Audio/MPEG-2 Video Integrated Decoder manufactured by ST Microelectronics, Inc., Carrollton, Tex. The decoder has a register interface
20
instead of a microcontroller. The register interface
20
is coupled to an external microcontroller
24
. The use of a register interface
20
makes it possible to tailor the decoder
10
to the specific hardware with which the decoder
10
interfaces, or to change its operation without having to replace the decoder by just reprogramming the register interface. It also allows the user to replace the microcontroller
24
, to upgrade or tailor the microcontroller
24
to a specific use, by just replacing the microcontroller and reprogramming the register interface
20
, without having to replace the decoder
10
.
The memory interface
18
is coupled to a memory
22
. A typical MPEG decoder
10
requires 16 Mbits of memory to operate in the Main Profile at Main Level mode (MP at ML). This typically means that the decoder requires a 2 Mbyte memory. Memory
22
is dedicated to the MPEG decoder
10
and increases the price of adding a decoder
10
to the electronic system. In current technology, the cost of this additional dedicated memory
22
can be a significant percentage of the cost of the decoder.
An encoder also requires a memory interface
18
and dedicated memory. Adding the encoder to an electronic system again increases the price of the system by both the price of the encoder and its dedicated memory.
FIG. 1
c
shows a conventional decoder inserted in a computer architecture. A conventional computer generally includes a peripheral bus
170
to connect several necessary or optional components, such as a hard disk, a screen, etc. These peripherals are connected to bus
170
via interfaces (e.g., a display adapter
120
for the screen) which are provided directly on the computer's motherboard or on removable boards.
A Central Processing Unit (CPU)
152
communicates with bus
170
through an interface circuit
146
enabling a main memory
168
of the computer to be shared between CPU
152
and peripherals of bus
170
which might require it.
The decoder
10
is connected as a master periphereal to bus
170
, that is, it generates data transfers on the bus without involving CPU
152
. The decoder receives coded or compressed data CD from a source peripheral
122
, such as a hard disk or a compact disk read only memory (CD-ROM), and supplies decoded images to display adapter
120
. Recent display adapters make it possible to directly process the “YUV” (luminance and chrominance) image data normally supplied by a decoder, while a display adapter is normally designed to process “RGB” (red, green, blue) image information supplied by CPU
152
.
Display adapter
120
uses memory
12
-
1
for storing the image under display, which comes from the CPU
152
or from the decoder
10
. A conventional decoder
10
also uses dedicated memory
22
. This memory is typically divided into three image areas or buffers M
1
to M
3
and a buffer CDB where the compressed data are stored before they are processed. The three image buffers respectively contain an image under decoding and two previously decoded images.
FIG. 1
d
illustrates the use of buffers M
1
to M
3
in the decoding of a sequence of images I
0
, P
1
, B
2
, B
3
, P
4
, B
5
, B
6
, P
7
. I stands for a so-called “intra” image, whose compressed data directly corresponds to the image. P stands for a so-called “predicted” image, the reconstruction of which uses pixel blocks (or macroblocks) of a previously decoded image. Finally, B stands for a so-called “bidirectional” image, the reconstruction of which uses macroblocks of two previously decoded images. The intra and predicted images are likely to be used to reconstruct subsequent predicted and bidirectional images, while the bidirectional images are not used again.
Images I
0
and P
1
are respectively stored in buffers M
1
and M
2
during their decoding. The filling and the emptying of a buffer in
FIG. 1
d
are indicated by oblique lines. The decoding of image P
1
uses macroblocks of image I
0
. Image I
0
, stored in bu
Colavin Osvaldo
Diaz Raul Zegers
Owen Jefferson Eugene
Carlson David V.
Gossage Glenn
Jorgenson Lisa K.
STMicroelectronics Inc.
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