Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-02-02
2008-11-25
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07458039
ABSTRACT:
An electronic circuit, in particular a receiver circuit contains a chain of stream processing circuits (10a-c). The stream processing circuits (10a-c) have control parameter inputs for receiving control parameter values. In order to facilitate design of circuits that receive data with a variable block size, a control circuit (14) is included that selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions that specify the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c) from the chain. Each particular local control circuit (11) is arranged to receive at least part of the instructions and to apply parameter values from the instructions to its corresponding stream processing circuit (10a-c). The particular local control circuit (11) controls timing of control parameter updates using block sizes from the instructions by counting off block size dependent time intervals between times points of successive control parameter updates. As a result there is no need to adapt the design of the stream processing circuits (10a-c) to the block sizes.
REFERENCES:
Hasan et al., “A delay spread based low power reconfigurable FFT processor architecture for wireless receivers,” 2003 Proceedings Int'l Symposium on System-on-Chip, pp. 135-138.
Swanchara et al., “A methodical approach for stream -oriented configurable signal processing,” 1999 Proceedings 32ndAnnual Hawaii Int'l Conference on System Sciences, pp. 3-4.
Zhang et al., “Architectural evaluation of flexible digital signal processing for wireless receivers,” 2000 Record of 34thAsilomar Conference on Signals, Systems and Computers, pp. 78-83.
Mohebbi et al., “A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core,” 2003 IEEE, pp. 103-108.
De Bart Abraham Jan
Gruijters Paulus Wilhelmus Franciscus
Van Dalen Edwin Jan
Garbowski Leigh Marie
NXP B.V.
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