Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2000-03-08
2001-10-09
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S174000, C365S175000, C365S188000
Reexamination Certificate
active
06301147
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electronic semiconductor circuits which include tunnel diodes.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers have continuously faced the problems of space, power and cost. Semiconductors which can be manufactured to require less semiconductor die area, use less power, and cost less are usually more desirable than otherwise equivalent semiconductors which require more die area, use more power, and/or are more expensive.
While these problems are experienced across a broad range of semiconductor products, they are acutely felt in connection with the manufacture of static semiconductor random access memory (RAM) devices. Static semiconductor RAM includes a multiplicity of memory cells, wherein each memory cell stores a single bit of data so long as the RAM device remains energized. Static memory differs from dynamic memory in that data stored in the static memory remains valid without the need for refreshing. A continuing need exists for memory cells that can be implemented in smaller semiconductor die area, consume less power, and are inexpensive. Smaller memory cells lead to semiconductor memory circuits which are capable of storing more data and are often faster devices. However, shrinking a memory cell without impairing stability, speed, yield or power consumption parameters is a difficult task.
FIG. 1
shows a schematic diagram of conventional variations of a static RAM (SRAM) cell. A basic memory cell
10
includes cross-coupled drivers
12
. Each driver
12
has an I/O port
14
, and drivers
12
together form a bistable storage element that stores a single bit of data. Pass transistors
16
couple I/O ports
14
to bit (B) and bit-bar ({overscore (B)}) lines
18
and word lines (W)
20
. Drivers
12
couple to Vss, and loads
22
couple between Vcc and drivers
12
. Conventional variations in memory cell
10
differ from one another in their configurations for loads
22
.
One prior art memory cell
10
uses resistors
24
for loads
22
. When resistors
24
are used for loads
22
, memory cell
10
is referred to as a four-transistor memory cell. Lower valued resistors
24
are desirable in order to improve yield, reliability, and area requirements. In addition, lower valued resistors
24
promote stability and greater immunity to noise when the drive transistors
12
for which they are loads are in “off” states. Unfortunately, higher valued resistors are desirable to reduce standby power consumption and to improve the speed of operation. Moreover, higher valued resistors promote stability and greater noise immunity when the drive transistors
12
for which they are loads are in “on” states.
No single resistor value of a four-transistor memory cell promotes stability and noise immunity for both states of drive transistors
12
. Further, as cell size shrinks, reduced power consumption becomes more important for purposes of heat dissipation because a given amount of power is dissipated over the cell's die area. Accordingly, the use of resistive loads in memory cell
10
leads to undesirably high standby power consumption and to worsened stability, speed, yield and/or reliability characteristics as cell size shrinks. Yield problems translate into increased costs.
Another prior art memory cell
10
uses P-channel transistors
26
for loads
22
. When P-channel or other transistors are used for loads
22
, memory cell
10
is referred to as a six-transistor memory cell. P-channel transistors
26
solve many of the problems associated with resistors
24
. P-channel transistor
26
memory cell implementations consume a moderately low amount of power and can be manufactured reliably. However, P-channel transistors
26
require an undesirably large die area. A P-channel transistor typically requires the formation of an N-well diffusion into the substrate in which the P-type drain and source diffusions are formed, and this N-well diffusion occupies a large area. Moreover, the channel itself is typically larger than in a corresponding N-channel transistor due to lower hole mobility for the P-channel device.
In addition, P-channel loads
26
cause the memory cells to experience current spikes for brief instants when both drive and load transistors are at least partially in their “on” states. The current spikes contribute to an undesirable package resonance effect and slow memory cell access, particularly for write operations. Accordingly, while P-channel transistor loads
26
work well for many purposes, P-channel transistors
26
are too large for use in small memory cells and experience excessive current spikes which slow operation and increase power consumption above theoretical levels.
Another prior art memory cell
10
uses depletion mode, N-channel transistors
28
for loads
22
. Depletion mode, N-channel transistors
28
are smaller than P-channel transistors
26
, but experience problems similar to those experienced by resistors
24
. In particular, depletion mode transistors
28
are characterized by high power in their “off” state. Processes which minimize this power consumption parameter cause yield problems. Moreover, a body effect causes a depletion mode transistor to continuously, rather than discretely or distinctly, transition between “on” and “off” states. This continuous transition feature leads to undesirable switching noise, current spikes, and slow access times.
Another prior art memory cell (not shown) uses a tunnel diode as a storage element. A tunnel diode has two distinct operating regions. A first operating region occurs at a low forward voltage, typically less than 0.1 volts. A second operating region occurs at a higher forward voltage, typically greater than 0.6 volts. The region between these two operating regions (i.e. typically around 0.1-0.6 volts) is an unstable region in which the device exhibits a negative resistance. A tunnel diode acts as a storage element by distinctly operating in either the first region or the second region. While a tunnel diode storage element exhibits desirable size and power characteristics, it is not a stable device. In other words, the tunnel diode storage element too easily switches to its other region of operation when a device incorporating such elements experiences a range of temperatures and read-write operations over time, as occurs in normal memory circuits. Because of stability problems, memory cells using tunnel diodes as storage elements have not proven themselves to be commercially viable.
Another problem with memory cells and other electronic semiconductor circuits relates to the excessive area requirements for interconnections between circuit components. For example, an interconnection connects load
22
with driver
12
in the prior art circuit of FIG.
1
. Other interconnections connect driver
12
with other components of the circuit, and still other interconnections connect still other components together. In a typical scenario, a contact area is provided in a top active semiconductor layer for respective nodes of each component. An insulating layer overlies the active semiconductor layers, but has vias or holes down to the contact areas. Metallization is applied over the insulating layer and into the vias, then etched so that the remaining metallization interconnects the electronic components.
An undesirable amount of circuit area is often consumed to provide contact areas. The contact areas usually need to be relatively large because the subsequent processing steps of forming vias and applying metallization may not precisely align axes of vias with centers of contact areas and require the bottom of vias to exhibit some minimum area to insure reliable and adequate fill-in by the metallization. Accordingly, the use of contact areas, vias and metallization to form interconnections consumes an undesirable amount of circuit area.
Furthermore, in order to prevent shorting to other interconnects, semiconductor devices should observe a minimum metal-to-metal spacing. In modern semiconductor processes, this metal-to-metal
El-Sharawy El-Badawy Amien
Hashemi Majid M.
Gresham, Esq. Lowell W.
Meschkow & Gresham P.L.C.
Meschkow, Esq. Jordan M.
National Scientific Corporation
Nguyen Viet Q.
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