Electronic programmable read-only-memory including a charge...

Details Electronic programmable read-only-memory including a charge... Electronic programmable read-only-memory including a charge...

1996-10-01

2001-10-09

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S336000, C257S408000

Reexamination Certificate

active

06300662

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to electronic programmable read-only-memories (EPROMs) and methods for fabricating EPROMs using sub-micron complementary metal oxide silicon (CMOS) processing techniques.
As is known in the art, EPROMs have a wide range of applications. One such EPROM device, here an ultraviolet (UV) erasable EPROM cell
10
′, is shown in
FIG. 1
to include a pair of heavily doped, here N+, source and drain regions
12
′,
14
′ formed in a field oxide
11
′ isolated P type conductivity well
16
′ of a P type conductivity silicon body
18
′. A carrier channel
20
′, here having a length greater than a micron, is disposed between the pair of source and drain regions
12
′,
14
′. Disposed over the carrier channel
20
′ is a floating polycrystalline silicon gate
22
′ separated by dielectric layer
23
′ from the channel
20
′ and from a control gate
24
′ by a dielectric layer
26
′. The dielectric layer
23
′ is typically a thermally grown silicon dioxide layer used to form a gate oxide for dielectric separation between the floating gate
22
′ and the surface of the silicon, (i.e., to prevent the floating gate
26
′ from short circuiting the source and drain regions
12
′,
14
′). The dielectric layer
26
′ is typically silicon dioxide, or silicon dioxide and silicon nitride, used between the floating gate
22
′ and the control gate electrode
24
′. It is noted that: the floating gate
22
′ and the control gate
24
′ are disposed in a vertical, or self-aligned arrangement. The heavily doped source and drain regions
12
′,
14
′, together with the control gate electrode
24
′, are used for programming the logic state of the cell. More particularly, to program the cell, a relatively high positive voltage, i.e., 12 to 15 volts, is applied to the control gate electrode
24
′ relative to the drain region
14
′, with the source region
12
′ being grounded. This relatively high positive voltage produces a relatively high, vertically oriented, electric field near the drain region
14
′ of sufficient intensity to attract “hot” electrons generated near the doped drain region
14
′ through the gate oxide
23
′ into the floating gate
22
′. Thus, in this programmed state, (i.e., with “hot” electrons (i.e., carriers) in the floating gate
22
′,) the threshold voltage of the cell
10
′ is increased from its initial, UV erased state. Having been programmed, the cell
10
′ is now operated in a normal operating mode with a lower, i.e., 5 volt, control gate electrode voltage
24
′. The difference in threshold voltage of the cell
10
′ is detected to determine storage by the cell of either a logic 0 bit or a logic 1 bit. To remove the stored “hot” electrons from the floating gate, UV light is again directed onto the cell
10
′ through a passivation layer, not shown, over the surface of the cell
10
′ and through a UV transparent window, not shown, provided in a package, not shown.
As is also known in the art, use of such EPROMs with CMOS devices on a common silicon substrate have been used in a wide range of applications. For example, complementary metal oxide silicon (CMOS) devices have been used to form microprocessors and the EPROMs have been used for storage of calibration coefficients, storage of die identification number, in addition to program storage for the microprocessor. (A typical NMOS FET
30
′ used with a PMOS FET, not shown, to form CMOS devices, is shown in
FIG. 2.
) However, incorporation of an EPROM cell into a standard sub-micron CMOS process is difficult for a variety of reasons: Self-aligned polycrystalline silicon floating and control gate electrodes
22
′,
24
′ (
FIG. 1
) are not commonly used in CMOS processing; Because the channel length of the CMOS device is now less than a micron, control electrode voltages as low as 5 volts may result in “hot” electrons being generated thereby requiring the CMOS devices to include lightly doped “hot” electron suppression regions
15
′ shown in
FIG. 2
, to avoid high electric fields obtained with an abrupt drain-channel junction, as shown in FIG.
1
and thereby suppress generation of “hot” electrons; and, CMOS passivation layers may not allow UV to pass into the cell thereby preventing erasing of the bit stored by the cell.
SUMMARY OF THE INVENTION
In accordance with the present invention, an electronic programmable read-only-memory (EPROM) is provided having a field effect transistor (FET) the gate electrode thereof coupled to a capacitor adapted to store charge produced in a channel region of the transistor in response to a logic state programming voltage applied to the EPROM. The field effect transistor and the capacitor are formed in a common semiconductor body along with CMOS transistors. The field effect transistor of the EPROM and the CMOS transistors have relatively heavy doped source and drain regions separated by an oppositely doped channel region. A gate electrode is disposed over the channel region. Lightly doped regions, having the same conductivity type as the source and drain regions, extend laterally from the source and drain regions to peripheral regions of the channel region to suppress generation of “hot” electrons in the EPROM FET and the CMOS FETs. Additional, relatively heavy doped regions are selectively formed in the EPROM FET and are inhibited from being formed in the CMOS transistors. The relatively heavy doped regions have the same conductivity type as the source and drain regions and extend laterally from the source and drain regions, through and beyond the lightly doped regions, into the channel region. The charge storing capacitor is coupled to the gate electrode and is adapted to store charge produced in the channel region in response to a logic state programming voltage applied to the EPROM.
With such an arrangement, the additional, relatively heavily doped regions formed selectively in the EPROM FETs dominate the EPROM FET lightly doped “hot” electron suppression regions to thereby enable generation of “hot” electrons during programming of such EPROM. In a preferred embodiment, the additional, heavily doped regions are formed when heavily doped electrostatic discharge (ESD) regions are formed for devices coupled to contact pads to prevent electrostatic discharge effects from harming other devices in the circuit.
In accordance with another feature of the invention, a method of forming a electronic programmable read-only-memory is provided. The method includes the step of forming a semiconductor body having formed therein relatively lightly doped source and drain regions separated by a channel, and a gate electrode disposed over an inner portion of the channel, lightly doped regions extending from the source and drain regions to a region in the channel disposed under the gate electrode. A relatively heavy doped region is formed in a relatively lightly doped region to provide a relatively highly doped region from the source and drain regions to regions disposed under the gate electrode. A charge storing capacitor is formed coupled to the gate electrode, such charge storing capacitor being adapted to store charge produced in the channel in response to a logic state programming voltage applied between the body and one of the source and drain regions.


REFERENCES:
patent: 5046043 (1991-09-01), Miller et al.
patent: 5146300 (1992-09-01), Hamamoto et al.
patent: 5300799 (1994-04-01), Nakamura et al.
patent: 63-66967 (1988-03-01), None
patent: 6-132489 (1994-05-01), None

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