Electronic parts packaging structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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Details

C257S686000, C257S777000, C257SE21614, C257SE23085, C257SE25013

Reexamination Certificate

active

07545049

ABSTRACT:
An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.

REFERENCES:
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5780776 (1998-07-01), Noda
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 2001/0002727 (2001-06-01), Shiraishi et al.
patent: 2001/0004130 (2001-06-01), Higashi et al.
patent: 2002/0117743 (2002-08-01), Nakatani et al.
patent: 2003/0197285 (2003-10-01), Strandberg et al.
patent: 1 041 631 (2000-10-01), None
patent: 1 225 629 (2002-07-01), None
patent: 2000-323645 (2000-11-01), None
patent: 2001-177045 (2001-06-01), None
patent: 2003-007896 (2003-01-01), None
Japanese Office Action mailed May 15, 2007, and partial English translation thereof.

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