Electronic package with optimized circuitization pattern

Details Electronic package with optimized circuitization pattern Electronic package with optimized circuitization pattern

2006-08-08

2006-08-08

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S773000, C257S737000, C257S739000, C257S780000, C257S702000, C257S778000

Reexamination Certificate

active

07088008

ABSTRACT:
An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.

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