Electronic package with high density interconnect and...

Details Electronic package with high density interconnect and... Electronic package with high density interconnect and...

2001-05-15

2003-12-16

Vigushin, John B. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C361S777000, C257S786000

Reexamination Certificate

active

06664483

ABSTRACT:

TECHNICAL FIELD
Embodiments of the present invention relate generally to electronics packaging and, more particularly, to an electronic package that includes an integrated circuit die or an integrated circuit package coupled to a substrate with a high density interconnect, and to manufacturing methods related thereto.
BACKGROUND INFORMATION
Integrated circuits (ICs) are typically assembled into electronic packages by physically and electrically coupling them to a substrate made of organic or ceramic material. One or more IC packages can be physically and electrically coupled to a substrate such as a printed circuit board (PCB) or motherboard to form a higher level electronic package or “electronic assembly”. The “electronic assembly” can be part of an “electronic system”. An “electronic system” is broadly defined herein as any product comprising an “electronic assembly”. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding the packaging of ICs, where each new generation of packaging must provide increased performance while generally being smaller or more compact in size. As market forces drive equipment manufacturers to produce electronic systems with increased performance and decreased size, IC packaging accordingly also needs to support these requirements.
In addition, manufacturers of high-end IC's, such as processors, are experiencing increasing demand for IC packages that can accommodate a high number of terminals (also referred herein as “bumps”, “pads”, or “lands”) on the IC. As high-end IC's contain an increasing amount of internal circuitry, they likewise have an increasing number of terminals that need to be coupled to corresponding terminals on the IC package substrate. Some ICs have a relatively large number of input/output (I/O) terminals, as well as a large number of power and ground terminals.
An IC package substrate generally comprises a number of metal layers selectively patterned to provide metal interconnect lines (referred to herein as “traces”), and at least one electronic component mounted on one or more surfaces of the substrate. The electronic component or components are functionally connected to other elements of an electronic system through a hierarchy of electrically conductive paths that include the substrate traces. The substrate traces typically carry signals that are transmitted between the electronic components, such as ICs, of the system.
“Flip-chip technology, whether ball grid array (BGA) or pin grid array (PGA), is a widely known technique for coupling ICs to a substrate. In fabricating a FCBGA package, for example, the electrically conductive terminals or lands on the inverted “upper” surface of an IC component are soldered directly to corresponding lands of a die bond area on the surface of the substrate using reflowable solder bumps or balls.
In addition to using FCBGA technology to couple an individual IC die to a substrate, whether at the single IC package level or at a higher level such as a chip-on-board (COB) multi-chip module, it is also well known to use FCBGA to couple an IC package to a substrate such as a printed circuit board (PCB) or motherboard. Solder bumps, for example, can be employed between lands on the IC package and corresponding lands on the PCB.
As the internal circuitry of ICs, such as processors, increases in complexity and size, such IC's have increasingly higher density formations of bonding terminals or lands. Typically this is manifested in a high density formation of lands conducting input and/or output signals. In order for an IC having a dense formation of lands to be packaged on a substrate, the substrate needs to have a relatively high signal trace “escape density”. That is, the substrate mush have an increasingly higher density of signals traces per unit length along the edge of the die bond area, or per unit area of the die bond area, that need to be connected to the lands of the IC or the IC package.
Thus, IC substrates need to provide mounting terminals that provide a higher signal trace escape density to accommodate the high density formations of lands on IC's. However, current dimension design rules for IC substrates serve to limit reductions in the width and spacing of traces on IC substrates. They also limit reductions in the size of terminals on IC substrates.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for apparatus and methods for packaging an IC or an IC package on a substrate that provide increased density of substrate terminal patterns, while still conforming to current dimension design rules for terminal size and for the width and spacing of substrate traces.


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