Electronic package with bonded structure and method of making

Details Electronic package with bonded structure and method of making Electronic package with bonded structure and method of making

1999-10-28

2001-09-25

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Portion of housing of specific materials

C257S687000, C257S704000, C257S712000, C257S730000

Reexamination Certificate

active

06294831

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices and more particularly to a prevention of warp thereof during operation within an electronic package.
BACKGROUND OF THE INVENTION
Conventionally, as shown in
FIG. 10
, underfill
4
, a material with a high elastic coefficient, has been filled between a semiconductor chip
2
and an organic substrate
1
in a Ball Grid Array (BGA) module
3
designed for mounting a flip-chip-type semiconductor chip
2
on the organic substrate
1
. Such modules are typically referred to in the art as electronic packages. Since the thermal expansion coefficient of the semiconductor chip
2
is not the same as that of the organic substrate
1
, the semiconductor chip
1
and the organic substrate
2
, between which underfill
4
is sandwiched, are thermally expanded or shrunk independently under a change in temperature.
Accordingly, the behavior of these structures differs according to thermal coefficients of expansion of the semiconductor chip
2
and the substrate
1
. For example, as shown in the much exaggerated view in
FIG. 11
, the module
3
may be deformed because of a rise or drop in temperature. Consequently, a BGA solder joint of the assembled module
3
may break, such that faulty connections are generated, thus exerting an adverse effect on the product's reliability. For this reason, the development of an electronic package which is not as affected by a change in temperature is strongly desired.
Laid-Open Japanese Patent Publication No. 62-249429 describes a semiconductor package in which a semiconductor “pellet” is bonded to a substrate and capped by metal or ceramics. In this package, in order to improve the radiation of heat generated inside the semiconductor “pellet”, heat transfer from the semiconductor “pellet” to the cap is increased by putting the upper surface of the semiconductor “pellet” into contact with the inner surface of the cap, or through the medium of a space-filled metal. However, this publication does not mention a poor bonding between a substrate and a semiconductor chip, which is generated by warpage or deformation of the substrate caused by the difference in thermal expansion coefficient between the substrate and the semiconductor chip.
DISCLOSURE OF THE INVENTION
A primary object of the present invention is to enhance the semiconductor art.
Another object of the present invention is to prevent defective connections between a semiconductor device and substrate by reducing warpage and deformation of such structures caused by a change in temperature (e.g., during product operation).
According to one aspect of the present invention, there is provided an electronic package comprising a substrate having a first surface, a semiconductor chip having an outer surface and mounted on the first surface of the substrate, and a structure substantially covering at least the outer surface of the semiconductor chip and having substantially the same coefficient of thermal expansion as the substrate, the structure being bonded to the first surface of the substrate.
According to another aspect of the invention, there is provided an electronic package comprising a substrate having a first surface, a semiconductor chip having an outer surface and mounted on the first surface of the substrate, and a structure having substantially the same coefficient of thermal expansion as the substrate and including an open portion covering at least the outer surface of the semiconductor chip, the structure being located on the first surface of the substrate and bonded to the substrate and the semiconductor chip by an adhesive material located within the hollow part of the structure.
According to another aspect of the invention, there is provided a method comprising providing a circuitized substrate having a first surface, positioning a semiconductor chip having an outer surface on the substrate and electrically coupling the semiconductor chip thereto, and positioning a structure having an open portion on the first surface of the substrate such that the open portion contacts the outer surface of the chip, the structure having substantially the same coefficient of thermal expansion as the substrate.


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patent: 5324888 (1994-06-01), Tyler et al.
patent: 5473191 (1995-12-01), Tanaka
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patent: 5789810 (1998-08-01), Gross et al.
patent: 5889323 (1999-03-01), Tachibana
patent: 5909057 (1999-06-01), McCormick et al.
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Kotthaus et al., “Study of Isotropically Conductive Bondings Filled with Aggregates of Nano-Sized Ag-Particles”, IEEE Trans. on Components, Packaging, and Manu. Tech., pp. 15-20, Mar. 1997.*
Wong et al., “Fast-Flow Underfill Encapsulant: Flow Rate and Coefficient of Thermal Expansion”, IEEE Trans. on Components, Packaging, and Manu. Tech., pp. 360-364, Oct. 29-30, 1997.*
Schaefer et al. “Conductive Adhesives with Improved Thermomechanical Properties”, Proceedings of 3rd International Conf. on Adhesive Joining and Coating Tech. in Elec. Manu., pp. 278-281, Sep. 28-30, 1998.

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