Electronic package having flip chip integrated circuit and...

Details Electronic package having flip chip integrated circuit and... Electronic package having flip chip integrated circuit and...

2000-06-29

2002-03-12

Gaffin, Jeffrey (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S782000, C361S783000, C361S784000, C257S724000, C257S728000, C257S737000, C257S778000, C257S787000

Reexamination Certificate

active

06356453

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic packaging. More particularly, the present invention relates to a multi-component electronic package.
BACKGROUND OF THE INVENTION
As is well known to those of skill in the art, electronic devices such as cellular telephones employed a variety of electronic components. Typically, these electronic components included active chip components as well as passive chip components. An active chip component such as an integrated circuit was capable of performing an action such as execution of an instruction. In contrast, a passive chip component such as a resistor, capacitor, or inductor possessed a specific electrical characteristic yet was incapable of performing an action.
The passive chip components were not readily integratable into the active chip components. To illustrate, it was not economical to form all required resistors, capacitors, or inductors in an integrated circuit chip. For this reason, the active chip component was packaged into a package, hereinafter referred to as an IC package. The IC package and the passive chip components were then attached to the printed circuit mother board separate from one another.
As the art moved to smaller, lighter weight and less expensive electronic devices, passive chip components were combined with active chip components in a single package.
FIG. 1
is a cross-sectional view of a multi-component package
10
in accordance with the prior art.
Referring now to
FIG. 1
, package
10
included a laminate substrate
12
having an upper surface
12
U and a lower surface
12
L. Formed on upper surface
12
U were a plurality of traces
14
and a die attach metallization
16
. Formed on corresponding traces
14
were contacts
18
. An upper solder mask
20
covered upper surface
12
U of substrate
12
and traces
14
yet left contacts
18
and die attach metallization
16
exposed.
A lower surface
22
L of an active chip component
22
, e.g., an integrated circuit, was attached to upper surface
12
U, and, more particularly, to die attach metallization
16
, by adhesive
24
. Bond pads
26
on an upper surface
22
U of active chip component
22
were electrically connected to correspond contacts
18
by corresponding bond wires
28
.
Terminals
30
of a passive chip component
32
, e.g., a resistor, capacitor, or inductor, were electrically connected to corresponding contacts
18
by solder joints
34
. In addition to forming the electrical connections between terminals
30
and the corresponding contacts
18
, solder joints
34
also served to mount passive chip component
32
to substrate
12
.
Active chip component
22
and passive chip component
32
were over molded in a layer of encapsulant
36
. Layer of encapsulant
36
served to protect the electrical connections of package
10
as well as to protect package
10
from the ambient environment, e.g., moisture.
Traces
14
were electrically connected to corresponding traces
38
on lower surface
12
L of substrate
12
by electrically conductive vias
40
. Contacts
42
were formed on corresponding traces
38
. A lower solder mask
44
covered lower surface
12
L of substrate
12
and traces
38
yet left contacts
42
exposed.
Formed on contacts
42
were corresponding solder balls
46
. As is well known to those of skill in the art, solder balls
46
were reflowed to attach and electrically connect package
10
to the printed circuit mother board. Solder joints
34
were formed of a solder having a higher melting temperature than that of solder balls
46
thus avoiding melting of solder joints
34
during reflow of solder balls
46
. Solder balls
46
were arranged in an array format to form a ball grid array (BGA) package. Alternatively, a land grid array (LGA) or leadless chip carrier (LCC) package was formed.
By integrating passive chip component
32
with active chip component
22
into a single package
10
, several advantages were realized as compared to attaching passive chip component
32
and active chip component
22
separately to the printed circuit mother board. One advantage was that less labor was required during component attachment to the printed circuit mother board. As a result, the cost of the electronic device employing package
10
was reduced. Another advantage was a reduction in final functional device size. However, when compared to a standard IC package containing only a single active chip component, package
10
was considerably larger, had reduced electrical performance and was significantly more expensive.
To minimize the cost associated with package
10
, package
10
was often fabricated simultaneous with a plurality of packages
10
in an array format.
FIG. 2
is a cross-sectional view of an array
50
of packages during fabrication in accordance with the prior art. Array
50
included a substrate
52
. Substrate
52
included a plurality of individual substrates
12
integrally connected together. Substrate
52
was fabricated using well-known techniques.
Passive chip components
32
were then attached to each individual substrate
12
. To illustrate, a first passive chip component
32
A of the plurality of passive chip components
32
was attached to a first substrate
12
A of the plurality of substrates
12
.
To attach passive chip component
32
A, solder paste was screened onto the appropriate contacts
18
on substrate
12
A in a well-known manner. The solder paste included both solder and solder flux. Passive chip component
32
A was positioned such that terminals
30
were aligned with and in contact with the screened solder paste. The screened solder paste was reflowed (melted) to mount passive chip component
32
A to substrate
12
A. The other passive chip components
32
were mounted to corresponding substrates
12
in a similar manner.
Since solder joints
34
were used to mount passive chip components
32
to corresponding substrates
12
, a sufficient amount of solder paste had to be used to insure that solder joints
34
reliably mounted passive chip components
32
. For the same reason, the solder flux of the solder paste was an aggressive, i.e., ionically active, solder flux.
Disadvantageously, the relatively large volume of solder paste contained a relatively large volume of aggressive solder flux. After mounting of passive chip components
32
, a substantial amount of solder flux residue
52
from the solder flux remained. More particularly, solder flux residue
52
was left as a contaminant around solder joints
34
and on solder mask
20
. Solder flux residue
52
was removed, e.g., using an aqueous cleaner.
FIG. 3
is a cross-sectional view of array
50
at a further stage during fabrication. Referring now to
FIG. 3
, active chip components
22
were attached to each individual substrate
12
by adhesives
24
. To illustrate, a first active chip component
22
A of the plurality of active chip components
22
was attached to first substrate
12
A by a first adhesive
24
A of the plurality of adhesives
24
.
Bond pads
26
of active chip component
22
A were then electrically connected to corresponding contacts
18
by corresponding bond wires
28
. Bond pads
26
were wirebonded to contacts
18
by bond wires
28
sequentially. The other active chip components
22
were mounted and wirebonded in a similar manner. Typically, active chip components
22
were placed sequentially, adhesives
24
were cured, and bond pads
26
were sequentially wirebonded to contacts
18
by bond wires
28
for each active chip component
22
.
FIG. 4
is a cross-sectional view of array
50
at a further stage during fabrication. Referring now to
FIG. 4
, a layer of encapsulant
56
was applied generally to cover an upper surface
52
U of substrate
52
. More particularly, layer of encapsulant
56
covered active chip components
22
including bond pads
26
, bond wires
28
, contacts
18
, solder mask
20
, passive chip components
32
including terminals
30
and solder joints
34
. Illustratively, layer of encapsulant
56
was a liquid encapsulant formed using a liquid encap

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