Electronic memory device

Details Electronic memory device Electronic memory device

2000-12-26

2002-04-02

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S189090, C365S226000, C365S230060, C365S189110

Reexamination Certificate

active

06366510

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an electronic memory device having electrically programmable memory cells, an address bus for addressing the memory cells, and a controllable programming voltage pump for producing a programming voltage for the memory cells.
Electronic memory devices of this kind are generally produced on a semiconductor chip containing, for example, an EEPROM module (Electrically Erasable Programmable Read-Only Memory) having an EEPROM array and a programmable voltage pump, and also a further module which has decoding and logic circuits and to which the inputs and outputs of the chip are connected. In this context, the memory array represents the actual memory and includes a configuration made up of a plurality of memory cells.
To program the individual EEPROM memory cells, a programming voltage of, for example, 20 V needs to be applied to them, where the programming voltage is much higher than the supply voltage of, for example, 5 V. The optimum programming voltage is obtained on the chip from the supply voltage using the regulated voltage pump.
EP-A 0 594 294 has disclosed an electronic memory device which has electrically programmable memory cells, an address bus for addressing the memory cells and also a controllable programming voltage pump for producing a programming voltage for the memory cells.
After such a semiconductor chip has been manufactured, the EEPROM needs, amongst other things, to be tested for its operability. For this, special programming commands used to program the memory array are provided.
In one of these tests, the programming voltage is lowered to a particular value, for example, in order to check whether the memory cells are just short of being reprogrammed at this programming voltage.
This programming voltage is supplied to the semiconductor chip externally via an additional test pad. This test pad is not required for normal operation of the memory device, however, and takes up chip area which is not available for enlarging the storage capacity, or makes the chip larger than it would actually need to be.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an electronic memory device of the type mentioned in the introduction in which the aforementioned test pad is not necessary for carrying out the operational test on the memory.
With the foregoing and other objects in view there is provided, in accordance with the invention an electronic memory device including electrically programmable memory cells; an address bus for addressing the memory cells; a controllable programming voltage pump for producing a programming voltage for the memory cells; and a switching device configured for actuation in a test mode by a test mode signal and for connecting the address bus to the programming voltage pump in the test mode such that the programming voltage can be set to a predetermined test programming voltage using address bits supplied on the address bus.
In particular, the electronic memory device mentioned in the introduction is provided with a switching device which can be actuated by means of a test mode signal and can be used to connect the address bus to the programming voltage pump in a test mode such that a predetermined or prescribable test programming voltage can be set using supplied address bits.
One advantage of this solution is that the use of the address bits in the command structure of the chip means that no additional complexity is necessary in the command decoder or in the control logic in order to transmit the nominal variable to the programming voltage pump.
In addition, in the case in which security-related data is stored in the memory, the absence of the test pad removes a point of access for a potential hacker. The test commands can be permanently locked in the chip before it leaves the factory, so that no further manipulation is possible.
Finally, the memory device requires less space on the chip, which means that the storage density of the chip can be increased for the same dimensions, or the chip can be made smaller for the same storage capacity.
Accordingly, the test programming voltage which can be prescribed is, in particular, a voltage at which the memory cells, in the fault-free state, are just short of being reprogrammable.
In accordance with an added feature of the invention, the memory cells preferably form an EEPROM array. However, other memory types in which a programming voltage is required in order to change the memory content and needs to be varied for test purposes are also possible.
In accordance with an additional feature of the invention, the prescribable test programming voltage can be set in the test mode preferably using a programming command.
In accordance with another feature of the invention, the switching device is a multiplexer.
In accordance with a further feature of the invention, the programming voltage pump is regulated, so that a nominal variable for the test programming voltage can be prescribed in the test mode using the address bits.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an electronic memory device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


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patent: 5615159 (1997-03-01), Roohparvar
patent: 5650734 (1997-07-01), Chu et al.
patent: 5765185 (1998-06-01), Lambrache et al.
patent: 5801989 (1998-09-01), Lee et al.
patent: 6154851 (2000-11-01), Sher et al.
patent: 0 594 294 (1994-04-01), None
patent: 411134886 (1999-05-01), None

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