Electronic memory addressing device especially for a memory orga

Details Electronic memory addressing device especially for a memory orga Electronic memory addressing device especially for a memory orga

1995-06-20

1998-05-05

Moore, David K.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711 1, 711 2, 711202, 711220, 711217, G06F 1210, G06F 1202

Patent

active

057490856

ABSTRACT:
A first and a second input ports, the sum of whose inputs is greater than an integer n, receive pairs of first words of k bits and of second words of n-k bits, each set of n bits representing an address item (ADI) for a point (PO) of a two-dimensional space of points (IM) associated with data coded on 2.sup.d bits, the respective bits of the first and second words representing two coordinates (X, Y) of the point in the said space. A configuration input receives a value of k (k1, k2, k3), chosen to be positive or zero and less than or equal to n, and representative of a (IM). Addressing means, which can be controlled through the value of k, select the inputs of the first port receiving the k bits of each first word and the inputs of the second port receiving the n-k bits of each second word, and form, from the selected bits, a cell address word of n bits making it possible to address the memory cell of the memory (MM) in which the datum associated with the said point will be stored.

REFERENCES:
patent: 3996559 (1976-12-01), Morrin et al.
patent: 4090174 (1978-05-01), Van Voorhis
patent: 4370732 (1983-01-01), Koggs
patent: 4400768 (1983-08-01), Christopher
patent: 5173947 (1992-12-01), Chande et al.
patent: 5269010 (1993-12-01), MacDonald
Proceedings of the 1985 International Conference On Parallel Processing Aug. 20, 1985, Washington, IEEE Comp. Soc. Press.
Proceedings of the 1985 International Conference on Parallel Processing. Aug. 20, 1985, Washington, IEEE Comp. Soc. Press.

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