Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2001-04-23
2004-11-23
Thai, Xuan M. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S112000, C710S113000, C370S400000
Reexamination Certificate
active
06823408
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims priority from Japanese Application No. P2000-128127 filed Apr. 27, 2000, the disclosure of which is hereby incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates to electronic equipment provided with a physical layer circuit constituting a physical layer which conforms to the IEEE 1394 standard, and a method for controlling the state of the physical layer circuit.
More specifically, the present invention relates to electronic equipment in which the physical layer circuit is operated in such a manner that, when receiving a first signal from a child node, the physical layer circuit changes its state from a first state into a second state and sends a first signal to a parent node, and when receiving a third signal for canceling the first signal from the child node before receiving the second signal corresponding to the first signal from the parent node, the physical layer circuit sends the third signal to the parent node after receiving the second signal from the parent node, and furthermore, the physical layer circuit returns its state from the second state to the first state after receiving the third signal from the parent node, thereby avoiding the occurrence of trouble which may be caused if the physical layer circuit receives the second signal from the parent node in the first state.
The present invention also relates to electronic equipment in which the physical layer circuit is operated in such a manner that, when receiving a first signal from a child node, the physical layer circuit changes its state from a first state into a second state and sends the first signal to a parent node, and when receiving a third signal for canceling the first signal from the child node after receiving the second signal corresponding to the first signal from the parent node and shifting its state from the second state to the third state, the physical layer circuit sends the third signal to the parent node, and furthermore, the physical layer circuit returns its state from the third state to the first state after receiving the third signal from the parent node, thereby avoiding the occurrence of trouble which may be caused if the physical layer circuit receives the second signal from the parent node in the first state.
As the standard defining the interface for supporting high-speed data transmission and real-time transmission as the interface for multimedia data transmission, the IEEE 1394 high-performance serial bus standard (the IEEE 1394 standard) is known. The IEEE 1394 standard defines data transmission at rates of 100 Mbps (98.304 Mbps), 200 Mbps (196.608 Mbps), and 400 Mbps (393.216 Mbps), and defines a 1394 port with higher transmission rate to have compatibility with its lower transmission rate. This standard allows data transmissions at rates of 100 Mbps, 200 Mbps, and 400 Mbps in one and the same network.
In addition, the IEEE 1394 standard employs a transmission format in the Data/Strobe link (DS-Link) coding method. In the transmission format in the Data/Stroke link coding method, as shown in
FIG. 1
, transmission data is converted into two signals including data and strobe for compensating the signal thereof, and the exclusive OR of these two signals is obtained, thereby generating clocks. The IEEE 1394 standard also defines a cable
200
having a structure such as shown in the cross-sectional view of
FIG. 2
, including: first shielding layers
201
; two pairs of twisted pair lines (i.e., signal lines)
202
, each shielded by a first shielding layer
201
; power supply lines
203
; and a second shielding layer
204
which entirely covers the cable constituted by tying the first shielding layers
201
, the twisted pair lines
202
, and the power supply lines
203
together.
The IEEE 1394 standard performs arbitration for obtaining a bus prior to data transmission, and, as a control signal for arbitration, defines an arbitration signal. In addition, the IEEE 1394 standard automatically reconfigures the entire bus topology by resetting the bus at the time when a node is added to or deleted from the bus. The arbitration signal is also defined as a control signal required for the topology reconfiguration.
The logical values of the arbitration signal in the physical layer are three values of “0”, “1”, and “Z”. These values are produced in accordance with the rules shown in Tables 1 and 2 below, and are decoded in accordance with the rule shown in Table 3 below.
TABLE 1
Transmit
arbitration
signal A
Drivers
(Arb_A_Tx)
Strb_Tx
Strb_Enable
Comments
Z
—
0
TPA driver is
disabled
0
0
1
TPA driver is
enabled,
strobe is low
1
1
1
TPA driver is
enabled,
strobe is high
TABLE 2
Transmit
arbitration
signal B
Drivers
(Arb_B_Tx)
Data_Tx
Data-Enable
Comments
Z
—
0
TPB driver is
disabled
0
0
1
TPB driver is
enabled,
data is low
1
1
1
TPB driver is
enabled,
data is high
TABLE 3
Received
Transmitted
arbitration
arbitration
Interpreted
comparator
signal for
arbitration
value
this port
signal
(Arb_n
a
_Rx)
(Arb_n
a
_Tx)
(Arb_n
a
)
Comments
Z
Z
Z
If this port is
0
Z
0
transmitting a Z,
1
Z
1
then the received
signal will be
the same as
transmitted by
the port on the
other end of the
cable.
Z
0
1
If the comparator
is receiving a Z
while this port
is sending a 0,
then the other
port must be
sending a 1.
This is the first
half of the 1's
dominance rule.
0
0
0
The other port is
sending a 0 or a Z.
Z
1
1
The other port
must be sending a
0. This is the
other half of the
1's dominance
rule.
1
1
1
The other port is
sending a 1 or a Z.
a
“n” is “A” or “B”. This table applies to both signal pairs.
In addition, the physical layer encodes the line state by use of two transmission arbitration signals Arb_A_Tx and Arb_B_Tx in accordance with the rules shown in Table 4 below, and decodes the line state by use of receive arbitration signals Arb_A and Arb_B in accordance with the rules shown in Table 5 below.
TABLE 4
Arbitration transmit
(Arb_A_Tx)
(Arb_B_Tx)
Line state name
Comments
Z
Z
IDLE
sent to
indicate a
gap
Z
0
TX_REQUEST
sent to
parent to
request the
bus
TX_GRANT
sent to child
when bus is
granted
0
Z
TX_PARENT_NOTI-
sent to
FY
parent
candidate
during
tree-ID
0
1
TX_DATA_PREFIX
sent before
any packet
data and
between
blocks of
packet data
in the case of
concatenated
subactions
1
Z
TX_CHILD_NOTIFY
sent to
child to
acknowledge
the parent
notify
TX_IDENT_DONE
sent to
parent to
indicate that
self-ID is
complete
1
0
TX_DATA_END
sent at the
end of
packet
transmission
1
1
BUS_RESET
sent to force
a bus re-
configuration
TABLE 5
Interpreted
arbitration signals
(Arb_A)
(Arb_B)
Line state name
Comments
Z
Z
IDLE
the attached
peer PHY is
inactive
Z
0
RX_PARENT_NOTIFY
the attached
peer PHY
wants to be
a child
RX_REQUEST_CANCEL
attached peer
PHY has
abandoned a
request (this
PHY is sending
a grant)
Z
1
RX_IDENT_DONE
the child PHY
has completed
its self-ID
0
Z
RX_SELF_ID_GRANT
the parent PHY
is granting the
bus for a
self-ID
RX_REQUEST
a child PHY is
requesting
the bus
0
0
RX_ROOT_CONTENTION
the attached
peer PHY and
this PHY both
want to be
child
RX_GRANT
the parent PHY
is granting
control of
the bus
0
1
RX_PARENT_HANDSHAKE
attached peer
PHY acknow-
ledges parent
notify
RX_DATA_END
the attached
peer PHY has
finished
sending a block
of data is
about to release
the bus
1
Z
RX_CHILD_HANDSHAKE
attached peer
PHY
acknowledges
TX_CHILD_
NOTIFY (the
peer PHY is
a child of
this PHY)
1
0
RX_DATA_PREFIX
the attached
per PHY is
about to
send packet
data or has
finished
sending a block
of packet data
and is about to
send more
1
1
BUS_RESET
send to force
a bus recon-
figuration
By use of the arbitration signals described above, the topology is automatically configured through the bus initialization phase, tree identification phase, and self-identification phase in this order.
At the bus initialization phase, the bus reset signal changes all the nodes into particular states, to entirely clear the topology information. As a result of the bus initialization, each node has information only about whether the node itself is a br
Nakamura Akira
Sato Tetsuya
Lerner David Littenberg Krumholz & Mentlik LLP
Sony Corporation
Thai Xuan M.
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