Electronic digital clock distribution system

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

326101, 327295, 327304, H03K 1900

Patent

active

056274823

ABSTRACT:
More particularly, an electronic digital clock distribution system provides a plurality of working rank clock signals to respective ones of a plurality of logic circuits. Each clock signal has a predetermined frequency and each logic circuit requires a working rank clock signal having a predetermined level of electrical power. An oscillator produces a master clock signal at the predetermined frequency and at an electrical power level at least equal to the sum of the power requirements for all working rank clock signals of the plurality of logic circuits. An electronic splitter network is connected to the oscillator to splitting the master clock signal into the plurality of working rank clock signals.

REFERENCES:
patent: 3851098 (1974-11-01), Pingault
patent: 4638256 (1987-01-01), Hong et al.
patent: 5140184 (1992-08-01), Hamamoto et al.
patent: 5172330 (1992-12-01), Watanabe et al.
patent: 5239215 (1993-08-01), Yamaguchi
patent: 5254886 (1993-10-01), El-Ayat et al.
patent: 5306959 (1994-04-01), Knauft et al.
patent: 5307381 (1994-04-01), Ahuja
patent: 5361277 (1994-11-01), Grover
patent: 5371417 (1994-12-01), Mirov et al.
patent: 5391942 (1995-02-01), El-Ayat et al.
patent: 5398262 (1995-03-01), Ahuja
patent: 5450024 (1995-09-01), Ruegg
Abstract-"Topological design of clock distribution networks based on non-zero clock skew specifications", Neves, J.L., Friedman, E.G., Proceedings of the 36th Midwest Symposium on Circuits and Systems, Aug. 16-18, 1993.
Abstract -"Clock distribution in general VLSI circuits", Ramanathan, P. Dupont, A.J.; Shin, K. G., IEEE Transactions Circuits and Systems I: Fundamental Theory and Applications, vol. 41, No. 5, May 1994.
Abstract -"Synchronous global clock distribution on multichip modules using optical waveguides", Koh, S.; Carter, H.W.; Boyd, J.T., Optical Engineering, vol. 33, No. 5, May 1994.
Abstract -"A new method for clock distribution", Grover, W. D., IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 41, No. 2, Feb. 1994.
Abstract -"High reliability PLL based clock distribution", Rogers, A.C., Wescon/92 Conference Record, Nov. 17-19, 1992.
Abstract -"Synchronous optical clock distribution for optoelectronic interconnections", Schwider, J. et al.; Optics Letters, vol. 19, No. 2, Jan. 15, 1994.
Abstract -"A comparative study of clock distribution approaches for WSI", Nigam, N.: Keezer, D.C., 1993 Proceedings, Fifth Annual IEEE International Conference on Wafer Scale Integration, Jan. 20-22, 1993.
Abstract -"High-speed clock distribution architecture employing PLL for 0.6 mu m CMOS SOG", Ishibashi, A.; Maeda, A.; Arakawa, T.; Higashitani, K.; Tatsuki, M., Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, May 3-6, 1992.
Abstract -"ECL: the technology of choice for your clock distribution needs", Pearson, T., Wescon Conference Record, Nov. 19-21, 1991.
Abstract -"High speed clock distribution schemes-a critical comparison", Sfarti, A., Wescon Conference Record, Nov. 19-21, 1991.
Abstract -"Solving clock distribution problems in high speed systems", Frederick, R., Wescon Conference Record, Nov. 19-21, 1991.
Abstract -"Active compensation of interconnection losses for multi-GHz clock distribution networks", Bussmann, M.; Langmann, U., IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing, vol. 39, No. 11, Nov. 1992.
Abstract -"A graph theoretic approach to the clock distribution problem", Mukund, P.R.; Bouldin, D. W., Proceedings, Fourth Annual IEEE International ASIC Conference and Exhibit, Sep. 23-27, 1991.
Abstract -"ASIC clock distribution using a phase locked loop (PLL)", Ashby, L., Proceedings, Fourth Annual IEEE International ASIC Conference and Exhibit, Sep. 23-27, 1991.
Abstract -"A low power clock distribution scheme for complex IC system", Ta, P.D.; Do, K., Proceedings, Fourth Annual IEEE International ASIC Conference and Exhibit, Sep. 23-27, 1991.
Abstract -"Fanout analysis of multi-stage optical clock distribution using opticalamplifiers", Li, C.-S.; Tong, F.; Liu, K.; Messerschmitt, D. G., IEEE Global Telecommunications Conference, vol. 1, Dec. 2-5, 1991.
Abstract -"Design and evaluation of wafer scale clock distribution", Keezer, D. C., Jain, V. K., Proceedings, International Conference on Wafer Scale Integration, Jan. 22-24, 1992.
Abstract -"Skew-free clock distribution for standard-cell VLSI designs", Blair, G.M., IEE Proceedings G (Circuits, Devices and Systems), vol. 139, No. 2, Apr. 1992.
Abstract -"Clock distribution strategies for WSI: a critical survey", Keezer, D.C.; Jain, V.K., 1991 Proceedings, International Conference on Wafer Scale Integration, Jan. 29-31, 1991.
Abstract -"Clock distribution design success with advanced logic", Morgan, R.J., Northcon/89 Conference Record, Oct. 17-19, 1989.
Abstract -"Clock distribution design success with advanced logic", Morgan, R.J., Wescon/89, Conference Record, Nov. 14-15, 1989.
Abstract -"A dynamically tracking clock distribution chip with skew control", Chengson, D.; Costantino, L.; Khan, A.; Le D., Yue L., Proceedings of the IEEE 1990 Custom Integrated Circuits Conference, May 13-16, 1990.
Abstract -"Design and verification of clock distribution in VLSI", Keezer, D.C., IEEE International Conference on Communications ICC '90 Including Supercomm Technical Sessions, Supercomm ICC'90 Conference Record, Apr. 16-19, 1990.
Abstract -"Harmonic series analysis of digital clock distribution circuits", Kraft, C., Proceedings of the 32nd Midwest Symposium on Circuit and Systems, Aug. 14-16, 1989, vol. 1.
Abstract -"Clock distribution for fast computer networks", Becke, G.; Last, W., Elektronik, vol. 39, No. 14, Jul. 6, 1990.
Abstract -"A clock distribution scheme for nonsymmetric VLSI circuits", Ramanathan, P.; Shin, K.G., 1989 IEEE International Clonference on Computer-Aided Design, Digest of Technical Papers, Nov. 5-9, 1989.
Abstract -"Design and fabrication of HOE for clock distribution in integrated circuits", Prongue, D.; Herzig, H.P., Second International Conference on Holographic Systems, Components and Applications (Conf. Publ. No. 311), Sep. 11-13, 1989.
Abstract -"High performance clock distribution for CMOS ASICs", Boon, S., Butler, S.; Bryne, R.; Setering, B.; Casalanda, M.; Scherf, A., Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, May 15-18, 1989.
"Fanout analysis of multi-stage optical clock distribution using opticalamplifiers", Li, C.-S.; Tong, F.; Liu, K.; Messerschmitt, D.G., IEEE Global Telecommunications Conference, vol. 1, Dec. 2-5, 1991.
"Synchronous optical clock distribution for optoelctronic interconnections", Schwider, J. et al. Optics Letters, vol. 19, No. 2, Jan.15, 1994.
"Synchronous global clock distribution on multichip modules using optical wageguides", Koh, S.; Carter, H.W.; Boyd, J.T., Optical Engineering, vol. 33, No. 5, May 1994.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electronic digital clock distribution system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic digital clock distribution system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic digital clock distribution system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2135068

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.