Electronic devices comprising thin film transistors

Details Electronic devices comprising thin film transistors Electronic devices comprising thin film transistors

2003-09-03

2004-06-08

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S949000

Reexamination Certificate

active

06746904

ABSTRACT:

The present invention relates to the manufacture of electronic devices comprising thin film transistors (TFTs) on an insulating surface, for example, a glass or insulating polymer substrate. The device may be, for example, an active matrix liquid crystal display (AMLCD) or other flat panel display.
For many years there has been considerable interest in developing thin-film circuits with TFTs on glass and/or on other inexpensive insulating substrates, for large area electronics applications. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form the switching elements of a cell matrix, for example, on the active plate of a flat panel display as described in U.S. Pat. No. 5,130,829.
Typically, the TFTs used in the active plate of a display have a lateral configuration, in that the source and drain electrodes are spaced laterally relative to the underlying substrate. The distance between these electrodes, which defines the channel length of the TFT, is determined using lithographic techniques. A uniform layer of electrode material is deposited, then patterned using photolithography and etching. Such processes are expensive as the associated equipment is costly and has a low throughput, and use large quantities of photoresist and developer. They are also difficult to control accurately across a relatively large substrate, for example, when fabricating LCDs for television applications. In addition, lithographic equipment currently available for use in manufacture is only able to reliably provide a minimum channel length of around 5 microns over a relatively large substrate. Shorter channel lengths are desirable as they result in higher speed TFTs.
In a vertical TFT, the source and drain electrodes are spaced normally relative to the substrate and the size of this spacing is defined by the thickness of one or more layers of the TFT, rather than by using photolithography.
A vertical TFT configuration is described in “Excimer-Laser-Produced Amorphous Silicon Vertical Thin Film Transistors” by Akihiko Saitoh and Masakiyo Matsumura, Jpn. J. Appl. Phys. Vol. 36 (1997) pp668-9. The process used to fabricate the TFT disclosed in this paper defines source and drain regions without employing photolithography, by laser crystallisation of amorphous silicon. However, photolithography is subsequently used to define the source and drain electrodes.
It is an object of the invention to provide an improved method of manufacturing an electronic device including a vertical thin film transistor.
The present invention provides a method of manufacturing an electronic device including a thin film transistor, comprising the steps of:
(a) forming a gate electrode on an insulating surface;
(b) depositing an insulating layer over the gate electrode and a region adjacent an edge of the gate electrode, such that the insulating layer comprises two outer surfaces which are substantially parallel to, and mutually spaced normally of, the insulating surface with a step extending therebetween;
(c) depositing a layer of semiconductor material;
(d) depositing a layer of electrode material;
(e) depositing a layer of negative resist material over the electrode material layer, the resist material being soluble in a predetermined solvent;
(f) irradiating the resist layer to render exposed portions insoluble in the predetermined solvent, the portion overlying the step being insufficiently exposed such that it remains soluble;
(g) developing the resist layer using the predetermined solvent, thereby removing the portion overlying the step; and
(h) removing the portion of the electrode material layer exposed by step (g) to define source and drain electrodes which extend over a respective one of the outer surfaces of the insulating layer to the step.
It may often be preferable to deposit the semiconductor layer before the electrode layer is deposited and patterned. For example, when using amorphous silicon, it is generally preferable to deposit it directly onto the insulating layer to provide a sound interface therebetween. However, in another preferred embodiment, step (c) of depositing the semiconductor layer is carried out after step (h). This is beneficial when using a semiconductor material which is not sufficiently resistant to the process used in step (h) to remove part of the electrode material layer. For example, polymeric semiconductors are not generally resistant to etchants likely to be used in patterning the electrode layer.
Preferably, the edge of the gate electrode is substantially normal to the insulating surface, resulting in a substantially vertical transistor channel. Nevertheless, it may be desirable to form the gate electrode edge at an angle to the substrate, forming a similarly angled transistor channel. It will be appreciated that in fabricating such a device according to the method of the invention, it will be necessary to adjust the angle of incidence of the radiation employed in step (e) so that the it is substantially aligned with the gate electrode edge.
A second thin film transistor may be formed simultaneously with the first thin film transistor at the edge of the gate electrode opposing the transistor channel of the first.
A low definition process may be used to define one or more, or all of the gate electrode and the other layers. As will be appreciated by the skilled person, photolithography is an example of a high definition process, whilst a low definition process may be a printing process such as gravure-offset printing, inkjet printing, or micro-dispensing. Photolithography requires the use of expensive vacuum equipment which has a relatively slow throughput. Low definition processes may often be achieved without the need for vacuum equipment. According to the method of the invention, the critical patterning step, that is the definition of the source and drain electrode spacing and therefore the TFT channel length, is achieved without the use of photolithography, and the use of vacuum equipment may be avoided. As the definition of the other TFT layers is generally less critical, it may be achieved with sufficient accuracy using relatively low cost, low definition processes. This particularly applies to AMLCDs with larger pixel sizes, such as a liquid crystal TV which may have a screen diagonal of greater than 20″ (510 mm). In a 25″ (635 mm) screen, a VGA display has a pixel size of 265×759 microns. In large pixels, the required channel aspect ratio, expressed as width divided by length, is large as well. Thus, the width of the channel may be defined by a relatively coarse definition process such as printing.
With printing techniques, materials are directly deposited in the required pattern, which avoids material wastage and may reduce the number of processing steps required. For example, resist materials may be printed onto layers of material deposited conventionally as a continuous blanket. Also, precursor materials may be printed onto a substrate and then converted into materials with the desired electrical properties by further processing steps.
The semiconductor material may comprise an organic, or more particularly, a polymeric material. These materials may be particularly suited to use in low definition processes such as printing or other low cost large area production techniques which may not require the use of expensive vacuum equipment, as they can be deposited in solution by techniques such as spin coating.
Preferably, the height of the upper surface of the gate electrode above the substrate is in the range of 0.05 to 1.5 microns. This in turn dictates the length of the transistor channel in the finished device.
Prior to the step of removing the portion of the electrode material layer exposed by the patterned resist layer, it may be advantageous to subject the resist layer to a reflow process and/or an ashing process, to improve the definition of the pattern in the resist layer.


REFERENCES:
patent: 5130829 (1992-07-01), Shannon
patent: 6414164 (2002-07-01), Afzali-Ardakani et al.
patent: 6461901 (2002-10-01), Noguchi
patent: 650417

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