Electronic device including discontinuous storage elements

Details Electronic device including discontinuous storage elements Electronic device including discontinuous storage elements

2007-04-17

2007-04-17

Tran, Long (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S332000, C257SE29257, C257SE29260, C438S270000, C438S212000, C438S243000, C977S707000, C977S712000

Reexamination Certificate

active

11188910

ABSTRACT:
An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein substantially none of the discontinuous storage elements lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and the primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.

REFERENCES:
patent: 4860070 (1989-08-01), Arimoto et al.
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 5721448 (1998-02-01), Hauf et al.
patent: 5824580 (1998-10-01), Hauf et al.
patent: 5914523 (1999-06-01), Bashir et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6074954 (2000-06-01), Lill et al.
patent: 6121148 (2000-09-01), Bashir et al.
patent: 6307782 (2001-10-01), Sadd et al.
patent: 6320784 (2001-11-01), Muralidhar et al.
patent: 6330184 (2001-12-01), White et al.
patent: 6399441 (2002-06-01), Ogura et al.
patent: 6583466 (2003-06-01), Lin et al.
patent: 6674120 (2004-01-01), Fujiwara
patent: 6706599 (2004-03-01), Sadd et al.
patent: 6818512 (2004-11-01), Hsieh
patent: 6894339 (2005-05-01), Fan
patent: 6916715 (2005-07-01), Hsiao et al.
patent: 6936887 (2005-08-01), Harari et al.
patent: 7098502 (2006-08-01), Mathew et al.
patent: 7015537 (2006-11-01), Lee
patent: 2002/0151136 (2002-10-01), Lin et al.
patent: 2003/0062565 (2003-04-01), Yamazaki
patent: 2003/0068864 (2003-04-01), Il-Young
patent: 2004/0000688 (2004-01-01), Harari et al.
patent: 2004/0121540 (2004-06-01), Lin
patent: 2004/0248371 (2004-12-01), Wang
patent: 2005/0037576 (2005-02-01), Chen et al.
patent: 2005/0148173 (2005-07-01), Shone
patent: 2005/0259475 (2005-11-01), Forbes
patent: 2005/0280089 (2005-12-01), Forbes
patent: 2005/0280094 (2005-12-01), Forbes
patent: 2006/0152978 (2006-07-01), Forbes
patent: 2006/0166443 (2006-07-01), Forbes
Guan, H., et al. “An Analytical Model for Optimization of Programming Efficiency and Uniformity of Split Gate Source-Side Injection Superflash Memory,” IEEE Transactions on Electron Devices, vol. 50, No. 3, pp. 809-815, Mar. 2003.
Hayashi, Y., et al. “Twin MONOS Cell with Dual Control Gates,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123, 2000.
Lee, D., et al. “Vertical Floating-Gate 4.5F2 Split-Gate NOR Flash Memory at 110nm Node,” 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 72-73, 2004.
Ma, Y. et al. “A Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories,” IEDM, p. 57-60, 1994.
Osabe, T. et al. “Charge-Injection Length in Silicon Nanocrystal Memory Cells,” 2004 Symposium on VLSI Technology Digest of Technical Papers p. 242-243, 2004.
Van Houdt, J., et al. “An Analytical Model for the Optimization of Source-Side Injection Flash EEPROM Devices,” IEEE Transactions on Electron Devices, vol. 42, No. 7, pp. 1314-1320, Jul. 1995.
U.S. Appl. No. 10/961,295, filed Oct. 8, 2004.
U.S. Appl. No. 11/079,674, filed Mar. 14, 2005.
U.S. Appl. No. 11/188,935, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,999, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,953, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,898, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,584, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,909, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,591, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,939, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,588, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,603, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,615, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,582, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,583, filed Jul. 25, 2005.
U.S. Appl. No. 11/188, 604, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,585, filed Jul. 25, 2005.
U.S. Appl. No. 11/525,747, filed Sep. 22, 2006.
U.S. Appl. No. 11/626,762, filed Jan. 24, 2007.
U.S. Appl. No. 11/626,753, filed Jan. 24, 2007.
U.S. Appl. No. 11/626,768, filed Jan. 24, 2007.

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