Electronic device including a conductive stud over a bonding...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S737000, C257S751000, C257S762000, C257SE21506, C257SE23023

Reexamination Certificate

active

07812448

ABSTRACT:
An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24). The process can also include forming a second barrier layer (52) overlying the conductive stud (34).

REFERENCES:
patent: 6426556 (2002-07-01), Lin
patent: 6531384 (2003-03-01), Kobayashi et al.
patent: 6803302 (2004-10-01), Pozer et al.
patent: 6943434 (2005-09-01), Tangpuz et al.
patent: 2002/0127836 (2002-09-01), Lin et al.
patent: 2003/0199159 (2003-10-01), Fan et al.
patent: 2004/0188851 (2004-09-01), Takewaki et al.
patent: 2006/0027933 (2006-02-01), Chen et al.
Liang, S.W., et al., “3-D Simulation on Current Density Distribution in Flip-Chip Solder Joints with Thick Cu UBM Under Current Stressing,” IEEE 2005 Electronic Components and Technology Conference, pp. 1416-1420.
Matsuki, H., et al., “Super CSP: A BGA Type Real Chip Size Package Using a New Encapsulation Method,” Pan Pacific Microelectronics Symposium, (3rd : 1998), pp. 415-419.
Murakami, N., et al., “Development of Real CSP Using Wafer Level Assembly Process,” in Proc. 4th VLSI Packag. Workshop, Kyoto, 1998, pp. 114-115.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electronic device including a conductive stud over a bonding... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic device including a conductive stud over a bonding..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic device including a conductive stud over a bonding... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4205921

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.