Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-05-31
2005-05-31
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S127000, C370S320000, C370S335000, C370S342000
Reexamination Certificate
active
06901492
ABSTRACT:
An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output data sets respectively associated with the N input data sets stored in the N elementary source memories at respective source addresses. The electronic device may also include N single port target memories, N interleaving tables including, for each relative source address, the number of a target memory and the respective target address thereof, N cells connected in a ring structure. Further, each cell may also be connected between an output of the processor, an interleaving table, and a target memory.
REFERENCES:
patent: 5761695 (1998-06-01), Maeda et al.
patent: 2003/0099217 (2003-05-01), Castor et al.
Patent abstract: Michael J. Thul et al. of Institute of Microelectronic Systems—University of Kaiserslautern, Germany and Lakshmi Rao of Dept. of Electrical and Computer Engineering—University of California, U.S.A. “Enabling High-Speed Turbo-Decoding Through Concurrent Interleaving”.
Berens Friedbert
Gilbert Franck
Thul Michael J.
Wehn Norbert
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Anderson Matthew D.
Jorgenson Lisa K.
STMicroelectronics N.V.
STMicroelectronics SA
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