Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-17
2001-11-20
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S342000, C257S401000
Reexamination Certificate
active
06320223
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an electronic device comprising a trench gate field effect device, particularly, but not exclusively, a trench insulated gate field effect power device such as a trench insulated gate power transistor.
U.S. Pat. No. 5,387,528 (our ref: PHB33804) describes an electronic device comprising a trench gate field effect device comprising a semiconductor body having first and second opposed major surfaces, and a trench extending into the first major surface so as to define at the first major surface a regular array of polygonal source cells each bounded by the trench. Each polygonal source cell contains a source region of one conductivity type and a body region of the opposite conductivity type with the body region separating the source regions from a common further region of the one conductivity type, generally a drain drift region. A gate extends within and along the trench for controlling a conduction channel through each of the body regions between the corresponding source region and the further region.
In order to increase the ruggedness of the device and to avoid undesired avalanche breakdown, each polygonal cell contains a central semiconductor region of the opposite conductivity type which is more highly doped than the body regions. This highly doped region controls the location of the avalanche breakdown in the polygonal source cells so that it is away from the trench gate and also delays switching of the diode formed by this region and the drain region of the device by controlling the hole current flow. This enables the onset of avalanche breakdown to be delayed until higher voltages and also allows the breakdown to be more controlled and reproducible from device to device.
Although such central highly doped regions improve the ruggedness of the device, the need for these central highly doped regions places an upper limit on the maximum number of cells per unit area of semiconductor that can be achieved which is lower than would otherwise be the case. Having a large number of source cells per unit area of the semiconductor is desirable because this increases the overall available channel width within the device and therefore enables a higher drain-source current and thus a lower specific ON resistance. This is particularly important for power switching capability. The specific ON resistance (R
DSon
) is defined as
V
DS
J
DS
·
A
Z
where V
DS
is the drain source voltage, J
DS
is the drain source current per unit length, A is the active device area (that is excluding any passive peripheral termination) and Z is the perimeter of the current flow along the device.
In order to enable the number of source cells per unit area to be increased, EP-A-0746030 proposes, as described with reference to FIG. 6 of EP-A-0746030, that the central semiconductor or ruggedness region be omitted from the source cells and that 1 in N of the source cells be replaced by an inactive cell that contains only the ruggedness or central semiconductor region, that is 1 in N of the cells has no source region and will not contribute to the current carrying capability of the device. Alternatively, as disclosed with reference to FIG. 13 of EP-A-0746030, the ruggedness or central semiconductor regions are again omitted from the source cells and, for every n source cells, a group of source cells (a group of four in the example shown in FIG. 13
b
) are replaced by a single, large ruggedness cell which is active, that is it contains a source region, and also contains a central or ruggedness region. However, this requires, as discussed with reference to
FIG. 13
, that the ruggedness cells be larger than the remaining cells thus reducing the overall channel width and causing the specific ON resistance to be higher that which would have been possible if the ruggedness cells were not present.
SUMMARY OF THE INVENTION
It is an aim of the present invention to provide an electronic device comprising a trench gate field effect device which enables the device to be rugged whilst also providing for a reduced specific ON resistance.
In one aspect, the present invention provides an electronic device comprising a trench gate field effect device having a regular array of polygonal source cells each containing a source region and a body region and each being bounded by a trench containing a gate for controlling conduction through a conduction channel area of the body regions between the source regions of the source cells and a further region of the device with the trench defining, for each polygonal source cell, an inner and an outer trench boundary with the inner trench boundary bounding a relatively highly doped region of opposite conductivity to the further region for increasing the ruggedness of the device and the area between the inner and outer trench boundaries being separated into a plurality of irregular subsidiary source cells by portions of the trench radiating outwardly from the inner to the outer trench boundary.
In one aspect, the present invention provides an electronic device comprising a trench gate field effect device having a regular array of polygonal source cells each containing a source region and a body region and each being bounded by a trench containing a gate for controlling conduction through a conduction channel area of the body regions between the source regions and a further region of the device with the trench defining, for each polygonal source cell, an inner and an outer trench boundary with the inner trench boundary bounding a relatively highly doped region of opposite conductivity to the further region for increasing the ruggedness of the device and the area between the inner and outer trench boundaries being separated into a plurality of subsidiary source cells by portions of the trench radiating outwardly from the inner to the outer trench boundary with the subsidiary source cells being of a different shape from the shape of the area bounded by the inner trench boundary.
In one aspect, the present invention provides an electronic device comprising a trench gate field effect device as set out in claim
1
.
Where the device is an enhancement mode device, then the body regions will be of opposite conductivity type to the source regions.
An electronic device comprising a trench gate field effect device in accordance with the present invention enables each polygonal source cell to have a relatively highly doped semiconductor region for improving the ruggedness of the device while also allowing the device to have a low specific ON resistance by increasing the overall channel width of the device by dividing the source cell into a plurality of subsidiary source cells using trench portions radiating outwardly from the inner to the outer trench boundary so that each of the trench portions defines part of the gate of the field effect device and contributes to the overall channel width and thus the overall current carrying capability of the device.
Various preferred features in accordance with the invention are set out in the dependent claims.
In an embodiment, there is provided an electronic device comprising a trench gate field effect device, comprising a semiconductor body having first and second opposed major surfaces, a trench extending into the first major surface so as to define at the first major surface a regular array of regular polygonal source cells each bounded by the trench, each source cell containing a source region and a body region with the body regions separating the source regions from a common further region, and a gate extending within and along said trench for controlling a conduction channel through each of the body regions between the corresponding source region and the further region, each source cell containing a central semiconductor region which is of opposite conductivity type to the further region and which is more highly doped than said body regions, wherein, for each polygonal source cell, said trench defines inner and outer coaxial trench boundaries with the inner trench boundary bounding a central subsi
Brown Adam R.
Gajda Mark
Hodgskiss Stephen W.
Hueting Raymond J. E.
Schligtenhorst Holger
Biren Steven R.
Prenty Mark V.
U.S. Philips Corporation
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