Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-05-23
2002-06-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S159000, C438S161000
Reexamination Certificate
active
06410411
ABSTRACT:
This invention relates to electronic devices, for example flat panel displays, and other types of large-area electronic device, comprising a thin-film circuit element. The invention also relates to methods of manufacturing such an electronic device.
There is currently much interest in developing thin-film circuits with thin-film transistors (hereinafter termed “TFTs”) and/or other semiconductor circuit elements on glass and on other inexpensive insulating substrates, for large-area electronics applications. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form the switching elements in a cell matrix, for example in a flat panel display as described in United States Patent Specification U.S. Pat. No. 5,130,829 (Our Ref: PHB 33646), and/or in integrated drive circuits for such cell matrices. Thin-film diodes (hereinafter termed “TFDs”) in the form of non-linear switching elements may be used instead of TFTs for the cell matrix of a display device, for example as described in published European Patent Application EP-A-0 649 048 (Our Ref: PHN 14613). United States Patent Specification U.S. Pat. No. 5,272,370 (Our Ref: PHB 33725) describes an example of a different type of large-area electronic device having an array of thin-film circuit elements, in this case a thin-film ROM device comprising different types of TFD having different conduction characteristics to determine the information content of the ROM array. The whole contents of U.S. Pat. No. 5,130,829, EP-A-0 649 048 and U.S. Pat. No. 5,272,370 are hereby incorporated herein as reference material.
In the development and manufacture of large-area electronic devices, it is recognized that the performance of the device can depend critically on the quality of the electrical contact between an electrode and a conductive film of a thin-film circuit element. There is a need to be able to form good quality contacts reproducibly and hence uniformly. A variety of materials are known for the electrodes and conductive films, for example as disclosed in U.S. Pat. No. 5,130,829, EP-A-0 649 048 and U.S. Pat. No. 5,272,370. In most cases the active area of a thin-film circuit element is a semiconductor conductive film most usually of silicon in an amorphous or microcrystalline or polycrystalline form or of a silicon-rich silicon compound. The silicon-based regions may be contacted by electrodes of, for example, chromium, tungsten, zinc, titanium, nickel, molybdenum, aluminium, and indium tin oxide (ITO). These electrodes may themselves be contacted by a conductive film (for example of aluminium, tungsten, molybdenum or ITO) which forms a pattern of interconnection tracks between these circuit elements. In most situations it is desirable for the electrode to make an ohmic contact of low resistance with the semiconductor and with the connection track, although in some cases the requirement is for a Schottky barrier of good quality.
The conference paper “An Ohmic Contact Formation Method for Fabricating &agr;-Si TFTs on Large Size Substrates” by Yukawa et al published in Proceedings of the 9th International Display Research Conference, Oct. 16-18, 1989, Kyoto, Japan, Japan Display '89, pages 506-509 describes previous difficulties in making uniform low-resistance contacts for bottom drain and source electrodes to the silicon film of a top-gate TFT. These difficulties had resulted in most flat panel displays being formed with bottom-gate TFTs, in spite of the many advantages of top-gate TFTs. The conference paper describes the avoidance of these difficulties by using ITO for the source and drain electrodes and by doping the silicon film with phosphorus from the ITO source and drain electrode patterns. Thus, in the method described in the conference paper, a film of ITO deposited on the device substrate is etched to form a desired pattern of pixel electrodes and source and drain electrodes and tracks for the TFTs, and this ITO pattern is then exposed to an RF glow discharge of PH
3
(phosphine). As a result of this phosphine plasma exposure, phosphorus dopant is adhered to the surface of the ITO pattern but not significantly to the SiO
2
surface layer of the substrate exposed between the ITO pattern. After an optional etching stage, an undoped amorphous silicon film is then deposited to provide the channel region of the TFT. During this deposition, n+ regions are formed in the amorphous silicon film adjacent the ITO pattern by phosphorus diffusion from the surface of the ITO. This doping of the semiconductor film from the ITO source and drain electrodes results in a good quality low resistance ohmic contact for the source and drain electrodes of the TFT. However, the need to deposit the silicon material on ITO does limit the deposition parameters, for example, to deposition temperatures of less than 250° C. Furthermore, some source gas compositions with a hydrogen gas content as commonly used for silicon deposition (for example SiH
4
with H
2
) are preferably not used with this process in order to prevent undesirable interactions with the ITO (for example hydrogen reduction of the ITO). If these limitations are not respected, surface decomposition of the ITO can occur, and the quality of the silicon film can be degraded by impurity diffusion from the ITO.
A top-gate TFT having source and drain electrodes of ITO and in which doped regions are formed in the overlying semi-conductor layer in similar manner through diffusion of phosphorus dopant contained in the ITO is described in EP-B-0 221 361. In this TFT, the ITO source and drain electrodes are formed also with tapered side walls.
It is an aim of the present invention to provide an electrode material suitable for forming good electrical contacts to semiconductor films and/or other conductive films used in thin-film processing for large-area electronic devices, while easing the limitations imposed on the thin-film process parameters.
According to one aspect of the present invention there is provided an electronic device including a thin-film circuit element which comprises an electrode in electrical contact with a conductive film (for example, of a silicon-based material or other semiconductor-based material), characterised in that the electrode comprises a film of chromium nitride.
The present invention is based on the discovery by the present inventors that chromium nitride surprisingly has a particularly advantageous combination of properties for use as an electrode material of thin-film circuit elements. Films of crystalline amorphous chromium nitride with low tensile stress, a range of nitrogen contents and good film integrity can be readily and controllably deposited at low temperature, for example at room temperature, by low-cost reactive sputtering. Chromium nitride processing is compatible with current thin-film circuit element technologies. The chromium nitride films can be patterned using etchants already used in thin-film technology for etching chromium, for example with low-cost wet-etching processes using ammonium ceric nitrate with nitric acid and/or hydrochloric acid. The chromium nitride films are chemically less reactive than chromium itself, ITO and many other electrode materials. They have a low affinity for oxide growth but they still have a relatively high conductivity, as a result of which high resistance barrier interfaces to semiconductor regions and/or to metal conductor tracks can be avoided. A chromium nitride film can protect an underlying film against hydrogen reduction and can also act as an effective barrier against impurity diffusion so protecting semiconductor regions against indium and other impurities. Thus, the chromium nitride film can protect an overlying semiconductor film during deposition, against contamination from an underlying film pattern of, for example, ITO, aluminium, molybdenum or another conductive material. Furthermore, a chromium nitride film pattern can even be used to dope an adjacent semiconductor region with conductivity type determining dopant for example using the plasma doping process described
Deane Steven C.
French Ian D.
McGarvey Brian P.
Trainor Michael J.
Koninklijke Philips Electronics , N.V.
Niebling John F.
Simkovic Viktor
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