Electronic device and optical transmission module

Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant

Reexamination Certificate

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C257S788000, C257S790000, C257S795000

Reexamination Certificate

active

06635971

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an electronic device comprising a circuit substrate to which a semiconductor integrated circuit chip is connected by means of a flip chip method employing solder, and to an optical transmission module.
Soldering is widely employed in the assembly of conventional electronic components (devices). However, due to the need to make electronic devices highly dense, miniature and thin, reduction in terminal pitch is progressing rapidly as a result of miniaturization and of an increase in the number of package connecting terminals, but there have been difficulties with conventional soldering techniques in supplying solder accurately to minute electrodes.
Connection techniques for directly mounting a semiconductor integrated circuit chip on a circuit substrate have been developed, among which flip chip method connections (flip chip connections), in which an active chip face of a semiconductor integrated circuit chip is mounted so as to be oriented downward to face a circuit substrate, have become a prominent fabrication method that serves as a means of realizing an improvement in electrical characteristics and structural density.
However, with such a flip chip connection, since the thermal expansion coefficient of the circuit substrate is large in comparison with that of a semiconductor integrated circuit chip, the application of heat leads to a marked change in the shape of the circuit substrate and, in turn, to an increase in the stress on the connection portion thereof, which sometimes results in the connection breaking.
For this reason, conventional flip chip connections employ a resin between the semiconductor integrated circuit chip and the circuit substrate in order to reduce the extent of any change in the substrate shape, to thereby prevent the connection from being broken.
One example of such a flip chip connection is disclosed in Japanese Patent Application Laid-open No. H9-107003. The structure of this publication employs a circuit substrate that has substrate electrodes disposed so as to be capable of electrical connection with protruding electrodes, an electrically conductive binding agent being interposed between the protruding electrodes and these substrate electrodes, and a resin being interposed between the semiconductor integrated circuit chip and the circuit substrate. The process described in this publication forms protruding electrodes for terminal electrodes of the semiconductor integrated circuit chip, and an electrically conductive binding agent is affixed to the tips of these protruding electrodes using a transfer method. Here, the transfer method is a method according to which protruding electrodes are pressed into an electrically conductive binding agent which is contained in a container to a predetermined depth, and, upon vertically raising these protruding electrodes, the electrically conductive binding agent of a predetermined depth is transferred to the protruding electrodes. Next, a resin is applied to the section of the circuit substrate upon which the semiconductor integrated circuit chip is mounted, and the semiconductor integrated circuit chip is mounted atop the circuit substrate from above the resin and then is heat-cured.
In addition, another flip chip method is disclosed in Japanese Patent Application Laid-open No. H8-172114. The structure described in this publication is constituted by forming protruding electrodes for terminals of a semiconductor integrated circuit chip, and solder is employed for the electrodes of the semiconductor substrate, which solder is melted and connected to the protruding electrodes. The process described in this publication involves forming protruding electrodes for terminal electrodes of the semiconductor integrated circuit chip, applying resin to the section on the circuit substrate upon which this semiconductor integrated circuit chip is to be mounted, mounting the semiconductor integrated circuit chip from above the resin, and applying pressure to and heating the semiconductor integrated circuit chip.
These conventional flip chip connection structures are such that, as shown in
FIG. 5
, one variety of resin
8
is employed to bind a semiconductor integrated circuit chip
1
and a circuit substrate
3
, such that the resin
8
provided between the semiconductor integrated circuit chip
1
and the circuit substrate
3
, and the resin
8
provided at the outer perimeter of the semiconductor integrated circuit chip are the same, there being no particular regulation of the modulus of elasticity of the resin.
Further, as shown in
FIG. 8
, one example, in which a resin
8
a
is provided between the semiconductor integrated circuit chip
1
and the circuit substrate
3
and a different resin
8
b
is provided at the outer perimeter of the semiconductor integrated circuit chip, is disclosed in the Japanese Patent Application Laid-open No. 2000-327884. This publication features the use of a resin
8
a
provided between the semiconductor integrated circuit chip
1
and the circuit substrate
3
that contains: (A) epoxy resin: 100 parts by weight, (B) polyorgano silsequioxane 100 to 300 parts by weight, and (C) curing accelerator: 0.01 to 10 parts by weight, and a resin
8
b
provided at the outer perimeter of the semiconductor integrated circuit chip
1
, which is subject to no particular limitations, but for which preferred materials are: epoxy resins, epoxy resins having the same components as the resin
8
&agr; provided between the semiconductor integrated circuit chip
1
and the circuit substrate
3
, and epoxy resins having an expansion coefficient below the glass transition temperature of no more than 20 ppm/° C.
Furthermore, another example in which a resin
8
a
is provided between a semiconductor integrated circuit chip
1
and a circuit substrate
3
, and a different resin
8
b
is provided at the outer perimeter of the semiconductor integrated circuit chip
1
is disclosed in the Japanese Patent Application Laid-open No. 2001-35884. This publication features the provision of a resin film between the semiconductor integrated circuit chip
1
and the circuit substrate
3
, and a method of covering the outer perimeter of the semiconductor integrated circuit chip
1
or the whole of the semiconductor integrated circuit chip
1
with an insulating resin.
Further, a structure, which is related to the present invention, appears in Japanese Patent Application Laid-open No. H4-137641.
SUMMARY OF THE INVENTION
The techniques disclosed in the above-referenced Japanese Patent Application Laid-open No. H8-172114 and Japanese Patent Application Laid-open No. H9-107003 exhibit problems outlined below due to the fact that one variety of resin is employed for the binding of a semiconductor integrated circuit chip and a circuit substrate, such that the resin provided between the semiconductor integrated circuit chip and the circuit substrate, and the resin provided at the outer perimeter of the semiconductor integrated circuit chip are the same.
In other words, in a case where a resin
6
of low elasticity is employed as the resin, as shown in
FIG. 6
, when heat is applied, the resin
6
of low elasticity cannot restrain a change in shape of the circuit substrate
3
, such that the circuit substrate
3
changes greatly in shape, and, as a result of the change in shape of the circuit substrate
3
, the connection portion is subjected to stress, which results in the connection breaking within a short time.
In addition, in a case where a resin of high elasticity
5
is employed as the resin, as shown in
FIG. 7
, when heat is applied, the resin of high elasticity
5
restrains a change in shape of the circuit substrate
3
, such that the change in shape of the circuit substrate
3
is limited. However, the stress on the edge portions
9
of the semiconductor integrated circuit chip is large. Further, separation occurs at the interface between the lateral faces of the semiconductor integrated circuit chip
1
and the resin
8
b
at the outer perimeter of the semiconduct

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