Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-08-06
2002-12-10
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S723000, C257S737000, C361S773000, C361S783000, C438S108000, C438S119000, C438S614000
Reexamination Certificate
active
06492737
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electronic device and a method of manufacturing the same. Particularly, the invention is concerned with a technique applicable effectively to an electronic device which adopts a flip-chip mounting technique.
BACKGROUND OF THE INVENTION
As an electronic device there is known an electronic device called MCM (Multi Chip Module). In MCM, plural semiconductor chips each incorporating an integrated circuit are mounted on a wiring board to implement one synthetic function. In connection with MCM, the adoption of a flip-chip mounting technique is becoming more and more popular in which a semiconductor chip (flip-chip) with salient electrodes formed on electrode pads on a circuit-formed surface is mounted onto a wiring board. This is for increasing the data transfer speed and for the reduction of size.
As to the flip-chip mounting technique, various mounting methods have been proposed and put to practical use. For example, mounting methods called CCB (Controlled Collapse Bonding) and ACF (Anisotropic Conductive Film) mounting are adopted practically.
In CCB method, solder bumps of, for example, a ball shape are formed as bump electrodes (salient electrodes) on electrode pads of a semiconductor chip, then the semiconductor chip is put on a wiring board, and thereafter a heat treatment for melting the solder bumps is performed to connect connection parts as wiring portions on the wiring board with the electrode pads of the semiconductor chip electrically and mechanically.
In ACF mounting method, stud bumps of such as gold (Au) are formed as bump electrodes (salient electrodes) on electrode pads of a semiconductor chip, then the semiconductor chip is put on a wiring board through an anisotropic conductive resin (ACF) of a sheet shape as a bonding resin, thereafter the semiconductor chip is compression-bonded to the wiring board under heating and the stud bumps are electrically connected to connection parts on the wiring board. The anisotropic conductive resin comprises an insulating resin and a large number of conductive particles dispersed and mixed therein.
SUMMARY OF THE INVENTION
Having studied the foregoing flip-chip mounting techniques, the present inventors found out the following problems.
(1) There are various types of arrays as pad arrays of a semiconductor chip. Among them is included a central pad array in which plural electrode pads are arranged in a line along a central region which extends along a center line in X or Y direction of a circuit-formed surface of a semiconductor chip. This central pad array is adopted, for example, for a semiconductor chip in which is incorporated a DRAM (Dynamic Random Access Memory) as a memory circuit.
For example in the case of a DRAM there are the following requirements with respect to the arrangement of electrode pads (bonding pads). Electrode pads should be arranged near an input/output circuit for the reduction of wiring inductance. Moreover, for the prevention of device damage in bonding process, a semiconductor device should not be formed just under electrode pads. Further, for the purpose of improving the operating speed, the distance from an input/output circuit up to a remotest portion in a memory mat should be made as short as possible. Satisfying these requirements results in such a layout on DRAM chip as shown in
FIG. 21
, in which electrode pads are arranged centrally in a long side direction of the chip. In
FIG. 21
, the numeral
30
denotes a DRAM chip, MARY denotes a memory array, PC denotes a peripheral circuit, I/O denotes an input/output circuit, and BP denotes an electrode pad.
In the case of a central pad array, the array of bump electrodes formed respectively on the electrodes pads is also a central bump array. If such a semiconductor chip is used in flip chip mounting, it is impossible to take balance of the chip, so that the chip tilts with respect to one main surface of a wiring board. Thus, in the case of a semiconductor chip having a central pad array, it is difficult to effect flip chip mounting. As another example of a pad array (bump array) with a semiconductor chip not well-balanced, there is, other than the central pad array, a one-side pad array (one-side bump array) in which plural electrodes pads are arranged in a line along one of two opposed sides of the chip.
(2) In ACF mounting method, stud bumps are compression-bonded to connection parts on a wiring board with a thermoshrinking force (a shrinking force developed upon return to a state of normal temperature from a heated state) or a thermocuring shrinking force (a shrinking force developed upon curing of a thermosetting resin) of an anisotropic conductive resin interposed between a wiring board and a semiconductor chip. On the other hand, since the thermal expansion coefficient of an anisotropic conductive resin is generally larger than that of stud bumps, the amount of expansion in the thickness direction of the anisotropic conductive resin is larger than that in the height direction of stud bumps. Consequently, there may occur a poor connection such that stud bumps come off from connection parts on the wiring board due to the influence of heat. Therefore, it is necessary that the volume of the anisotropic conductive resin between the wiring board and the semiconductor chip be made as small as possible.
In this connection, a technique for diminishing the volume of an anisotropic conductive resin between a wiring board and a semiconductor chip is disclosed, for example, in Japanese Published Unexamined Patent Application No. Hei 10(1998)-270496 (U.S. Pat. No. 6,208,525). According to the technique disclosed in this unexamined publication, as shown in
FIG. 12
thereof, “a groove
19
A is formed in a rigid wiring board
19
, electrode pads
4
A formed within the groove
19
A, and the electrode pads
4
A and bump electrodes
15
are connected together within the groove
19
. According to this configuration, a gap between the wiring board
19
and a semiconductor chip
10
becomes narrower by an amount corresponding to the depth of the groove
19
A in comparison with the case where there is no top insulating layer on the wiring board and the electrodes pads
4
A and a top wiring layer are exposed, whereby it is possible to reduce the thickness of an adhesive (anisotropic conductive resin)
16
interposed between the wiring board
19
and the semiconductor chip
10
.”
However, according to the above configuration wherein a groove is formed in a wiring board and electrode pads (connection parts) on the wiring board and bump electrodes (stud bumps) are connected together within the groove, there arises a new problem.
In the case of electrode pads on a semiconductor chip, a plane size depends on the array pitch of the electrode pads (a pad array pitch) and the narrower the pad array pitch, the smaller the plane size. If a thinner gold wire is used to form stud bumps of a smaller diameter with such a decrease in size of the electrode pads, the height of each stud bump also becomes smaller accordingly. That is, if the pad array pitch differs, the stud bump height differs as well.
On the other hand, in a certain electronic device, such as MCM, several types of semiconductor chips different in the degree of integration and in function are mounted on a single wiring board, but these semiconductor chips are not always equal in pad array pitch. With different pad array pitches, there are different stud bump heights, so in the case of a semiconductor chip wherein the stud bump height is larger than the depth from one main surface of a wiring board to connection parts thereof, it is possible to easily effect connection between the wiring board connection parts and the stud bumps, but in the case of a semiconductor chip wherein the stud bump height is smaller than the depth from one main surface of a wiring board to connection parts thereof, it is difficult to effect connection between the wiring board connection parts and the stud bumps.
If a depth position of the wiring board connection parts is set to mat
Imasu Satoshi
Kado Yoshiyuki
Kishikawa Norio
Naito Takahiro
Sato Toshihiko
Cuneo Kamand
Miles & Stockbridge P.C.
Vigushin John B.
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