Electronic design for integrated circuits based on process...

Details Electronic design for integrated circuits based on process... Electronic design for integrated circuits based on process...

2008-04-01

2008-04-01

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07353475

ABSTRACT:
A pattern-dependent model is used to predict variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variations to the integrated circuit and (b) a lithography or etch process, and an impact is determined of the variations of feature dimensions on electrical characteristics of the integrated circuit. An impact is determined of the topological variations on electrical characteristics of the integrated circuit. An RC extraction tool is used in conjunction with the using of the model and the determining of the impact.

REFERENCES:
patent: 5124927 (1992-06-01), Hopewell et al.
patent: 5581475 (1996-12-01), Majors
patent: 5597668 (1997-01-01), Nowak et al.
patent: 5663076 (1997-09-01), Rostoker et al.
patent: 5705301 (1998-01-01), Garza et al.
patent: 5763955 (1998-06-01), Findley et al.
patent: 5798298 (1998-08-01), Yang et al.
patent: 5821621 (1998-10-01), Jeng
patent: 5854125 (1998-12-01), Harvey
patent: 5861342 (1999-01-01), Gabriel et al.
patent: 5903469 (1999-05-01), Ho
patent: 5920487 (1999-07-01), Reich et al.
patent: 5923563 (1999-07-01), Lavin et al.
patent: 5923947 (1999-07-01), Sur
patent: 5948573 (1999-09-01), Takahashi
patent: 5972541 (1999-10-01), Sugasawara et al.
patent: 6049789 (2000-04-01), Frison et al.
patent: 6081272 (2000-06-01), Morimoto
patent: 6093631 (2000-07-01), Jaso
patent: 6109775 (2000-08-01), Tripathi et al.
patent: 6118137 (2000-09-01), Fulford et al.
patent: 6124197 (2000-09-01), Fulford
patent: 6157947 (2000-12-01), Watanabe et al.
patent: 6176992 (2001-01-01), Talieh
patent: 6230299 (2001-05-01), McSherry et al.
patent: 6249904 (2001-06-01), Cobb
patent: 6255125 (2001-07-01), Schmidt et al.
patent: 6259115 (2001-07-01), You et al.
patent: 6263476 (2001-07-01), Browen et al.
patent: 6289499 (2001-09-01), Rieger et al.
patent: 6309956 (2001-10-01), Chiang et al.
patent: 6323113 (2001-11-01), Gabriel et al.
patent: 6327555 (2001-12-01), Shimizu et al.
patent: 6328872 (2001-12-01), Talieh et al.
patent: 6343370 (2002-01-01), Taoka et al.
patent: 6344408 (2002-02-01), Chen et al.
patent: 6344409 (2002-02-01), Jaso
patent: 6352623 (2002-03-01), Volodarsky et al.
patent: 6355387 (2002-03-01), Fujinaga et al.
patent: 6380087 (2002-04-01), Gupta et al.
patent: 6396158 (2002-05-01), Travis
patent: 6486066 (2002-11-01), Cleeves et al.
patent: 6539321 (2003-03-01), Bruce et al.
patent: 6550041 (2003-04-01), McBride
patent: 6556884 (2003-04-01), Miller et al.
patent: 6556947 (2003-04-01), Scheiner et al.
patent: 6562639 (2003-05-01), Minvielle et al.
patent: 6567964 (2003-05-01), Shin et al.
patent: 6578174 (2003-06-01), Zizzo
patent: 6578188 (2003-06-01), Pang et al.
patent: 6611045 (2003-08-01), Travis et al.
patent: 6613688 (2003-09-01), Brown et al.
patent: 6625801 (2003-09-01), Pierrat et al.
patent: 6651226 (2003-11-01), Houge et al.
patent: 6660569 (2003-12-01), Barthelmess et al.
patent: 6665856 (2003-12-01), Pierrat et al.
patent: 6671570 (2003-12-01), Schulze
patent: 6781570 (2003-12-01), Schulze
patent: 6691297 (2004-02-01), Misaka et al.
patent: 6704920 (2004-03-01), Brill et al.
patent: 6708129 (2004-03-01), Pasadyn et al.
patent: 6708318 (2004-03-01), Satoh et al.
patent: 6742165 (2004-05-01), Lev et al.
patent: 6751785 (2004-06-01), Oh
patent: 6866974 (2005-03-01), Kim et al.
patent: 6873720 (2005-03-01), Cal et al.
patent: 6893800 (2005-05-01), Jessen et al.
patent: 6904581 (2005-06-01), Oh
patent: 7174520 (2007-02-01), White et al.
patent: 7243316 (2007-07-01), White et al.
patent: 2001/0031506 (2001-10-01), Plat et al.
patent: 2001/0052107 (2001-12-01), Anderson et al.
patent: 2002/0045110 (2002-04-01), Ohnuma
patent: 2002/0051567 (2002-05-01), Ganz et al.
patent: 2002/0083401 (2002-06-01), Breiner et al.
patent: 2002/0106837 (2002-08-01), Cleeves et al.
patent: 2002/0157076 (2002-10-01), Asakawa
patent: 2002/0162082 (2002-10-01), Cwynar et al.
patent: 2003/0084416 (2003-05-01), Dai et al.
patent: 2003/0107134 (2003-06-01), Lee
patent: 2003/0199150 (2003-10-01), Permana et al.
patent: 2003/0228714 (2003-12-01), Smith et al.
patent: 2003/0229410 (2003-12-01), Smith
patent: 2003/0229479 (2003-12-01), Smith et al.
patent: 2003/0229868 (2003-12-01), White et al.
patent: 2003/0229875 (2003-12-01), Smith et al.
patent: 2003/0229880 (2003-12-01), White et al.
patent: 2003/0229881 (2003-12-01), White et al.
patent: 2003/0237064 (2003-12-01), White et al.
patent: 2004/0044984 (2004-03-01), Keogan et al.
patent: 2004/0058255 (2004-03-01), Jessen et al.
patent: 2004/0076896 (2004-04-01), Kim et al.
patent: 2004/0107410 (2004-06-01), Misaka et al.
patent: 2005/0037522 (2005-02-01), Smith et al.
patent: 2005/0132306 (2005-06-01), Smith et al.
patent: 2005/0196964 (2005-09-01), Smith et al.
patent: 2005/0235246 (2005-10-01), White et al.
patent: 2005/0235248 (2005-10-01), Smith et al.
patent: 2005/0289500 (2005-12-01), Misaka et al.
patent: 0 453 753 (1991-10-01), None
patent: 03/079240 (2003-09-01), None
patent: 03/079240 (2003-09-01), None
Park et al. “Pattern Dependent Modeling of Electroplated Copper Profiles” 2001 IEEE.
Boning, Duane et al., “Statistical metrology of interlevel dielectric thickness variation,”Proceedings of the SPIE Symposium on Microelectronic Manufacturing, Oct. 1994, SPIE vol. 2334, pp. 316-327.
Boning, Duane et al., “Models for Pattern Dependencies: Capturing Effects in Oxide, STI, and Copper CMP,” Jul. 17, 2001, Semicon West.
Boning, D. et al, “Pattern Dependent Modeling for CMP Optimization and Control,” MRS Spring Meeting, Proc. Symposium P: Chemical Mechanical Polishing, San Francisco, CA, Apr. 1999.
Boning, Duane S. et al., “A General Semiconductor Process Modeling Framework,”IEEE Transactions on Semiconductor Manufacturing, vol. 5, No. 4, Nov. 1992, pp. 266-280.
Chen, Yu et al., “Monte-Carlo Algorithms for Layout Density Control,” Asia and South Pacific Design Automation Conference, Jan. 2002, pp. 523-528.
Chen, Yu et al., “Hierarchical Dummy Fill for Process Uniformity,” Asia and South Pacific Design Automation Conference, Jan. 2001, pp. 139-144.
Chen, Yu et al., “Practical Iterated Fill Synthesis for CMP Uniformity,” ACM/IEEE Design Automation Conference, Jun. 2000, pp. 671-674.
Davis, Joseph C. et al., “Automatic Synthesis of Equipment Recipes from Specified Wafer-State Transitions,”IEEE Transactions on Semiconductor Manufacturing, vol. 11, No. 4, Nov. 1998, pp. 527-536.
Hosack, Harold H. et al., “Recent Advances in Process Synthesis for Semiconductor Devices,”IEEE Transactions on Electron Devices, vol. 45, No. 3, Mar. 1998, pp. 626-633.
Kahng, Andrew B. et al., “New and Exact Filling Algorithms for Layout Density Control,” UCLA Department of Computer Science, Los Angeles, CA, 1999.
Kahng, Andrew B. et al., “Filling and Slotting: Analysis and Algorithms,” International Symposium on Physical Design, Monterey, CA, 1998, pp. 95-102.
Kahng, Andrew B. et al., “New Multilevel and Hierarchical Algorithms for Layout Density Control,” UCLA Department of Computer Science, Los Angeles, CA, 1999.
Kahng, Andrew B. et al., “Filling Algorithms and Analyses for Layout Density Control,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 4, Apr. 1999, pp. 445-462.
Kim, Yoo-Hyon et al., “CHAMPS (CHemicAl-Mechanical Planarization Simulator),” International Conference on Simulation of Semiconductor Processes and Devices, Seattle, WA, Sep. 6-8, 2000.
Lee, Keun-Ho, “Analyzing the Effects of Floating Dummy-Fills: From Feature Scale Analysis to Full-Chip RC Extraction,” Samsung Electronics Co., Ltd, Korea, 2001.
Lee, Brian et al, “Using Smart Dummy Fill and Selective Reverse Etchback for Pattern Density Equalization,”Proc. CMP-MIC, Santa Clara, CA, Mar. 2000, pp. 255-258.
McGhee, John et al., “The MMST Computer-Integrated Manufa

Affiliated with

Also associated with

Rating

Electronic design for integrated circuits based on process... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic design for integrated circuits based on process..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic design for integrated circuits based on process... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2782578