Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-02
2003-03-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06539536
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to the field of logic synthesis for integrated circuit devices. More particularly, aspects of the present invention relate to methods and apparatus for design for test within a logic synthesis system.
(2) Background of the Related Art
Complex integrated circuits are designed with the use of computer aided design (CAD) tools. Specifically, application specific integrated circuits (ASICs) and field programmable gate array (FPGA) circuits can be designed using a variety of CAD tools. The development of ASICs and FPGA circuits with the aid of CAD tools is referred to as electronic design automatic or EDA. Design, checking and testing of large scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly because the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also partly because considerable computation is required in order to achieve an efficient layout of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist generally of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures and functions. At the logic level, the descriptions of the circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer implemented compiler (also called a “silicon compiler”). The computer implemented compiler program processes this description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a “netlist.” The components of a netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches and D-flip flops, etc. and their interconnections used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order to generate a technology dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
An important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is known to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design and the special memory cells and associated circuitry are referred to as DFT implementations. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its “mission mode” circuitry while the portions added to the integrated circuit to facilitate testability are called “test mode” circuitry or DFT implementations. The resultant circuit therefore has two functional modes, mission and test.
An exemplary flow chart diagram of a typical logic synthesis process, including a DFT process, is shown in FIG.
1
. The processes
200
described with respect to this flow chart is implemented within a computer system in a CAD environment. High level design language (HDL) descriptions of the integrated circuit enter at block
201
. Also accompanying the HDL
201
is a set of performance constraints
205
applicable to the design which typically include timing, area, power consumption, and other performance related limitations that the compiler
225
will attempt to satisfy when synthesizing the integrated circuit design. Constraints
205
can also include non-performance related constraints such as structural and routing constraints. Compiler
225
consists of a generic compiler
203
(also called an HDL compiler, RTL synthesizer, or architectural optimizer) that inputs the HDL
201
description and generates therefrom a technology independent or “generic” netlist
207
which is also dependent on the constraints
205
. As discussed above, the netlist
207
is a list of technology independent components or operators and the interconnections between them.
The generic netlist
207
is then input to a design compiler
209
that includes a computer implemented logic optimization procedure and a mapping procedure which interfaces with a technology dependent cell library
230
(e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library
230
contains specific information regarding the cells of the specific technology selected such as the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in the library
230
. Logic optimization procedure of block
209
includes structuring and flattening procedures. The mapping procedure of block
209
generates a gate level mapped netlist
211
that is technology dependent having cells specifically selected to satisfy the constraints
205
. This gate level netlist
211
consists at this point of “mission mode” circuitry.
At block
212
of
FIG. 1
, DFT process
213
performs a particular test insertion process (here a scan) to implement testability cells or “test mode” cells into the overall integrated circuit design. In this process
213
, memory cells of the mapped netlist
211
are replaced with memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In one particular DFT process, these memory cells specially designed for test are called scannable memory cells. The test vector patterns can be derived from combinational or sequential automatic test pattern generation (ATPG) processes depending on whether or not a full or partial scan is performed by the scan insertion process
213
. Process
213
also performs linking groups of scannable memory cells into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process
213
is a scannable netlist
215
that contains bo
Ajjarapu Srinivas
Martin Denis
Singh Harbinder
Walker Robert
Do Thuan
Smith Matthew
Synopsys Inc.
Wagner , Murabito & Hao LLP
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