Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-11-22
2001-07-31
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S228000, C365S230060, C365S189090
Reexamination Certificate
active
06269032
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based on and incorporates herein by reference Japanese Patent Application No. 11-344811 filed Dec. 3, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic control unit (ECU) for controlling automobiles and/or automotive engines, and particularly to an improvement in a method of data writing to a stand-by random access memory (RAM), electrically-erasable programmable read-only memory (EEPROM) or the like to be provided in the relevant electronic control unit.
2. Related Art
GB2191613A (JP-A No. S62-258154) discloses a data backup apparatus. In this apparatus, if a constant voltage Vcc drops during a periodical writing process of data on the occasion of conducting the periodical writing of data, such a write process is instantaneously stopped and an interrupt process (routine) for saving the data is executed preferentially. Therefore, when the periodical write process is recovered after the end of interrupt process, it is thought that the SRAM write process is inhibited (restricted) in the course of such a write process. During this event, it is assumed that the data before and after the write process co-exist in the SRAM and erroneous write process is conducted.
For example, if the data before the write process and the data after the write process co-exist, the concurrency is lost in such a case as writing the data that requires concurrency such as combination of the timing for starting receiving an engine knock signal (gate opening time) and the timing for ending receiving the same (gate closing time).
Moreover, when there are many important data that must be saved for the data saving process accompanied by the most preferential interrupt process, a longer time is required for the data saving process. Accordingly, all data that requires the saving will not be written in the SRAM within the accessible time thereof.
In Japanese Unexamined Utility Model Publication No. S63-84800, when the constant voltage Vcc drop, the write operation of data in the course of writing to SRAM is continued and when writing of data is completed, such write operation is suspended. Therefore, also in the event that the data that requires concurrency is written, the concurrency of data is lost because the data writing is stopped in the course of the writing operation and the data after the end of data writing and the data before the start of data writing co-exist.
Thus, the vehicle or engine controllability is lessened when data is read from SRAM after recovery of the constant voltage for use in the control of engine or vehicle, if concurrency is lost for the data that requires the concurrency and the data is erroneously written.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an electronic control unit that can maintain the concurrency for writing of data that requires concurrency and simultaneously executes a write process of data to a memory.
According to the present invention, an electronic control unit comprises a power supply source, a CPU, a memory, a voltage detecting circuit and a signal output circuit.
In one aspect, the signal output circuit outputs to the memory a signal indicating an inhibition of data write operation after elapse of time from an input of a voltage-drop signal from the voltage detecting circuit. The time is determined to complete the write operation of data divided for each data having at least concurrency. The CPU permits a start of the write operation to the memory to execute the write operation of data for each data that requires concurrency when a signal output from the voltage-drop detecting circuit is other than the voltage-drop signal and a signal output from the signal output circuit indicates a permission of data write operation.
In another aspect, the signal output circuit generates a first signal that shifts to a data write inhibition condition from a data write permission condition after a predetermined time has passed from input of a voltage-drop signal from the voltage-drop detecting circuit and a second signal that shifts to the data write inhibition condition from the data write permission condition after elapse of time determined to complete the write operation of data divided for each data that requires at least concurrency after the shift of condition of the first signal. The signal output circuit further generates a second signal to the memory to restrict the data write operation. The CPU permits a start of the data write operation to the memory to execute the write operation of data for each data that requires the concurrency when both the first and second signals output from the signal output circuit indicate permission of the data write operation.
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Honda Takayoshi
Takeuchi Yoshiharu
Denso Corporation
Fears Terrell W.
Nixon & Vanderhye P.C.
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