Electronic control unit

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S011000, C714S704000, C714S706000

Reexamination Certificate

active

10788370

ABSTRACT:
First and second control circuit sections that mutually communicate via a series-parallel converter comprise first and second adder-subtracter respectively. When any receiving error occurs in each control circuit section, a variation value3is added to the adder-subtracter on the receiving side. When data is normally received, a variation value1is subtracted from the adder-subtracter. Initial value of the adder-subtracter is set to 9. When a current value exceeds 11, first and second error detection signal is generated to carry out alarm display or initialization, and initialization and restart of the other-side control circuit section.

REFERENCES:
patent: 4385383 (1983-05-01), Karchevski
patent: 4511958 (1985-04-01), Funk
patent: 5784274 (1998-07-01), Murayama et al.
patent: 6098179 (2000-08-01), Harter, Jr.
patent: 6393590 (2002-05-01), Wood et al.
patent: 6745120 (2004-06-01), Iwagami et al.
patent: 09-162814 (1997-06-01), None
patent: 09-219720 (1997-08-01), None
patent: 2000-267948 (2000-09-01), None
patent: 2002-108835 (2002-04-01), None
patent: 2002-235598 (2002-08-01), None

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