Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Reexamination Certificate
2002-01-16
2004-02-03
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
C257S686000, C257S694000, C257S695000, C257S786000
Reexamination Certificate
active
06686648
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention:
The invention relates to an electronic component with semiconductor chips that are stacked one on the other and a method for fabricating the component.
Electronic components are stacked to form larger hybrid units after the completion of each individual device with a semiconductor chip and a lead frame. Via the different lead frames the finished devices that are stacked one above the other are connected to form an electronic component with semiconductor chips stacked one on the other, wherein the outer flat conductors of the lead frames are connected to one another via corresponding external contact pins. Electronic components comprising stacked individual devices which are formed in this way have the disadvantage that they cannot be produced in a compact design, especially as each lead frame between the devices has a large space requirement.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an electronic component and a method for fabricating the component, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the advantages of planar technology can be used and wherein it is possible to obtain significantly more compact structures for electronic components comprising stacked individual parts.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electronic component, comprising:
a stack of a plurality of semiconductor chips each having an active top side and a sawn edge;
contact areas and interconnects formed on the active top side for rewiring to contact areas of respectively adjacent (overlying and/or underlying) semiconductor chips; and
the interconnects connecting to the contact areas on the active top side, extending toward the sawn edge of the semiconductor chip, and connecting to the respectively adjacent semiconductor chips via through-contacts formed at the sawn edge of the semiconductor chip.
In other words, the electronic component comprises semiconductor chips which are stacked one on the other and have, on their active top side, contact areas and interconnects for rewiring to contact areas of overlying or underlying semiconductor chips. To that end, the interconnects for rewiring are arranged on the top side of the semiconductor chip and connected to the contact areas. The interconnects for rewiring extend from the contact areas on the active top side of the semiconductor chips to the edges of the semiconductor chip and are connected to overlying and underlying semiconductor chips via through contacts, which are arranged on sawn edges of the semiconductor chip.
Such an electronic component has the advantage that a plurality of semiconductor chips which are stacked one on the other can be arranged without having to arrange complicated lead frames in between. Rather, the connections between semiconductor chips that are stacked one above the other are realized by the through contacts arranged on sawn edges of the semiconductor chip. This technology makes full use of the advantage of planar technology in that, before a wafer is actually divided, it is possible to complete all the through contacts in the region of the sawing tracks and through contacts are produced only when the wafer is divided into individual semiconductor chips, said through contacts being configured in circle segment form in cross section. The sawing ensures that the through contacts are arranged at the edge of each chip and are thus easily accessible for connection to the underlying interconnects for rewiring.
In one embodiment of the invention, the bottommost semiconductor chip has solder deposits instead of through contacts. In a further preferred embodiment of the invention, said deposits may be screen printing solder deposits. These solder deposits may have the effect that upon the emplacement of the next semiconductor chip and heating to soldering temperature the solder melt rises on account of capillary action in the through contact holes arranged at the edge of overlying semiconductor chips. To that end, the through contact holes have, on the one hand, an adhesion promoter layer and, on the other hand, a solderable coating, preferably made of copper, silver, gold or alloys thereof. These metals are distinguished by the fact that they are readily wettable and consequently exhibit a great capillary action for the through contacts.
In a further embodiment of the invention, a rewiring plane is in each case arranged between the stacked semiconductor chips. These rewiring planes in no way correspond to a lead frame of an electronic component with semiconductor chips. The rewiring plane is merely formed from the interconnects for rewiring, which, in a further embodiment of the invention, are arranged on an insulating layer on the active semiconductor top side. This insulating layer is patterned in such a way that the contact areas remain uncovered for access to the electronic circuits of the semiconductor chip and the interconnects can be applied unimpeded with relatively inexpensive means for rewiring. That also includes the screen printing of such interconnects on the insulating layer.
In a further embodiment of the invention, the through contacts themselves have an adhesion promoter layer on their inner wall, which layer may preferably be composed of titanium and/or a titanium alloy. Said adhesion promoter layer is intended to facilitate the transition from the semiconductor material to the soldering material and at the same time ensure that a solderable surface coating becomes possible on the inner wall of the through hole. As mentioned above, such an inner coating may again be formed from copper, silver or gold in order to improve the wetting with a solder material.
The insulating layer provided between the semiconductor chip surface and the interconnects for rewiring is preferably a polymer, in particular a polyimide layer.
Since the through contacts, the coating of the inner wall of the through contacts and the provision of the interconnects for rewiring can be carried out at a wafer level, i.e. simultaneously for many semiconductor chips, this electronic component has the advantage that it can predominantly be fabricated with the aid of planar technology. Through contacts on the sawn edges of the semiconductor chip are produced if care is taken to ensure that the through contacts are already present in the sawing tracks of the wafer before a saw blade whose thickness is less than the diameter of the through contacts separates the chips at their edges. Through contacts having circle segments in cross section are produced from the cylindrical through contacts during the separation process. If rectangular or triangular through contacts are incorporated into the semiconductor wafer, then after sawing pillar-type structures are produced which in each case have only part of the cross section of the originally introduced quadrangular and triangular pillars, since the central region of each pillar has been sawn out by the dividing operation.
In a further embodiment of the invention, the semiconductor chips comprise memory chips. In memory chips, in particular, there is a need to realize as far as possible a high volume density of memory locations, which is now possible by virtue of the apparatus according to the invention since all lead frames are obviated and no housing structures whatsoever enlarge the volume of the electronic component with stacked semiconductor chips.
Accordingly, the apparatus according to the invention makes it possible to realize extremely compact electronic components, and a further compacting effect can be achieved by thinning the semiconductor chips by grinding. To that end, thinning-by-grinding techniques are employed which reduce the initial thickness of a semiconductor wafer of approximately 500 to 800 &mgr;m by at least one order of magnitude to 50 to 80 &mgr;m, so that a semiconductor wafer having a thickness of hundreds of &mgr;m becomes a semiconductor chip of ten
Gebauer Uta
Wennemuth Ingo
Greenberg Laurence A.
Infineon - Technologies AG
Lebentritt Michael S.
Locher Ralph E.
Menz Doug
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