Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-08-30
2004-03-23
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000, C438S109000
Reexamination Certificate
active
06710455
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to an electronic component with at least two stacked semiconductor chips and a method for fabricating the same.
In many electronic components, a first semiconductor module, for instance a logic module, and a second semiconductor module, for instance a memory module, are needed. In order to save space on a printed circuit board (PCB), it makes sense to house both semiconductor chip modules in a common housing with an optimally low space requirement. A logic module typically has a square surface, and a memory module has a rectangular surface, so that when semiconductor modules are stacked as in a known chip-on-chip structure, the bond contact surfaces partly overlap. One solution to the problem is to dispose the two semiconductor modules side by side in one housing, which results in a substantial consumption of space. In an alternative solution, the two semiconductor modules are mounted in a lead frame housing, which is associated with a complex and difficult assembly, because the components must be turned several times with bond wires partly exposed. Another principle is also applied, according to which the semiconductor modules are mounted in different housings, which are then stacked. But this is a cost-intensive method, and furthermore, it leads to large mounting heights of the electronic component.
Published, Japanese Patent Application JP 08250651-A describes a semiconductor configuration in which two semiconductor modules are stacked in spaces that are separated by a dividing wall. Both semiconductor chip modules are connected with the aid of bond wires to external contacts by way of interconnects. The known semiconductor configuration takes up a relatively large component volume and is complicated and expensive to fabricate.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an electronic component with at least two stacked semiconductor chips and a method for fabricating the electronic component which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which is easy to build and inexpensive to fabricate, and which takes up a small space.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electronic component. The electronic component contains semiconductor chips including at least one first semiconductor chip and at least one second semiconductor chip. The first semiconductor chip has an active chip surface and a passive back side, and the second semiconductor chip has a passive back side. A stacking layer is disposed between the first semiconductor chip and the second semiconductor chip. A carrier substrate receives the semiconductor chips and has a top side. The passive back side of the first semiconductor chip is fastened to the top side of the carrier substrate. The passive back side of the second semiconductor chip is fastened to the active chip surface of the first semiconductor chip through the stacking layer. First bonding connections are formed for conductively connecting the first semiconductor chip to the top side of the carrier substrate. Second bonding connections are formed for conductively connecting the second semiconductor chip to the top side of the carrier substrate.
The electronic component inventively contains the first semiconductor chip, the second semiconductor chip as well as the carrier substrate for receiving the semiconductor chips.
A first passive back side of the first semiconductor chip is fastened on a top side of the carrier substrate. A second passive back side of the second semiconductor chip is fastened on a first active chip surface of the first semiconductor chip by way of a stacking layer. The first and second semiconductor chips are also conductively connected to the top side of the carrier substrate by first and second bond connections, respectively.
The inventive component has the advantage that two semiconductor modules with different outer dimensions can be housed in a common housing in an extremely space-efficient fashion by reason of the fact that the semiconductor chips are joined to one another.
It is thus possible to stack a square semiconductor chip with a rectangular semiconductor chip and vice versa, whereby the semiconductor chips only partly overlap, and whereby both semiconductor chips include regions protruding beyond the overlap, respectively. No feasible solution can be found in the prior art for such different outer dimensions.
An inventive embodiment provides that the first and second semiconductor chips are conductively connected to contact terminal pads on the top side of the carrier substrate by first and second bond wires. The stacking layer between the two semiconductor chips makes it possible to connect the first semiconductor chip to the carrier substrate with the aid of bond wires before the second semiconductor chip is mounted. The stacking layer has a height that guarantees a minimum spacing between the bond wires and the second semiconductor chip. The advantage of the embodiment is its highly compact construction that is also easy to fabricate.
In an embodiment of the invention, the first semiconductor chip has a first stacking surface on its first active chip surface. The first stacking surface is connected two-dimensionally to a second stacking surface on the second passive back side of the second semiconductor chip by way of the stacking layer. In this embodiment of the invention, it is possible to achieve a precisely defined spatial distribution of the stacked semiconductor chips, and therefore to conductively connect each semiconductor chip to the carrier substrate without the semiconductor chip which is mounted later being able to damage or squeeze the bond wires.
According to a preferred embodiment of the invention, the stacking layer contains an adhesive layer with particles embedded in it. The particles can be formed of ceramic powder and can provide for a defined spacing between the two semiconductor chips, i.e. a defined stacking layer height.
According to an alternative embodiment of the invention, the stacking layer contains an adhesive layer and an adhesive frame surrounding the adhesive layer. The adhesive frame provides for a defined height of the stacking layer and thus a defined spacing of the semiconductor chips from one another.
According to another embodiment of the invention, the carrier substrate is provided with external contacts on a bottom side, which is averted from the semiconductor chips, which contacts can be realized as contact bumps for flip-chip assembly, for example. This makes possible a rapid and cost-effective processing of the electronic component, which can be placed on a PCB and soldered thereto.
According to another development, the carrier substrate is constructed as a rewiring board. A three-dimensional rewiring structure can also be contained in the carrier substrate, as warranted, which gives the inventive electronic component highly compact dimensions.
The advantage of an electronic component that is built and fabricated according to the invention is the ability to reliably conductively connect a memory module with a rectangular shape and a logic module with a square shape in a small space.
A housing that covers the carrier substrate and surrounds the semiconductor chips can be constructed extremely flat and therefore highly compact.
An inventive method for fabricating an electronic component according to one of the foregoing embodiments includes the now described steps. A first semiconductor chip is prepared with a first stacking surface on a first active chip surface. A second semiconductor chip is prepared with a second stacking surface on a second passive back side. A carrier substrate which has at least one bearing surface and contact terminal pads on a top side is also prepared.
The first, passive back side of the first semiconductor chip is fastened to the bearing surface of the carrier substrate using a conductive adhesive layer or a solde
Goller Bernd
Hagen Robert-Christian
Ofner Gerald
Stümpfl Christian
Thumbs Josef
Clark Sheila V.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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