Electronic component package using multi-level lead frames

Details Electronic component package using multi-level lead frames Electronic component package using multi-level lead frames

1986-01-06

1989-01-31

Grimley, Arthur T.

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

29827, H01L 2302

Patent

active

048017655

ABSTRACT:
Disclosed is a semiconductor package with a high pin count. External contacts to the chip are provided by interdigitated leads formed from an upper and lower lead frame. The lower lead frame includes a paddle for mounting the chip. The upper lead frame initially has its leads tied together and a center portion is punched out to fit the size of the particular chip. The two lead frames are preferably coplanar in the area around the boundaries of the package encapsulant.

REFERENCES:
patent: 3271625 (1966-09-01), Caracciolo
patent: 3676748 (1972-07-01), Kobayashi et al.
patent: 4105861 (1978-08-01), Hascoe
patent: 4380042 (1983-04-01), Angelucci, Sr. et al.
patent: 4477828 (1984-10-01), Scherer
patent: 4496965 (1985-01-01), Orcutt et al.
patent: 4498122 (1985-02-01), Rainal
patent: 4542259 (1985-09-01), Butt
patent: 4579404 (1986-04-01), Lockard
patent: 4602831 (1986-07-01), Lockard
patent: 4677526 (1987-06-01), Muehling

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