Electronic clock

Details Electronic clock Electronic clock

1999-11-29

2002-04-30

Lee, Thomas (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S501000, C713S502000, C713S503000, C710S058000, C368S202000

Reexamination Certificate

active

06381702

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an electronic timepiece incorporating a microcomputer. More particularly, it relates to a highly accurate electronic timepiece in which the operation of a logical slowdown/speedup circuit for adjusting timepiece accuracy is controlled by a microcomputer.
Conventional electronic timepieces have utilized a quartz oscillation circuit of 32 kHz to perform logical slowdown/speedup on a cycle of 10 seconds. In this case, adjustment has been performed at an adjustment resolution of 1/32768×86400/10=264 msec./day, which value has created substantially no problem for accuracy of a monthly deviation of several tens of seconds. However, there has been a trend toward clocks of higher accuracy in the last few years, and electronic timepieces having high accuracy on the order of a yearly deviation of several tens of seconds have been developed.
In order to maintain an accuracy on the order of a yearly deviation of several tens of seconds, fine factory adjustment of accuracy is important, and the adjustment resolution of 264 msec./day has become ineffective.
Under such circumstances, various methods have been employed in high accuracy electronic timepieces to achieve finer adjustment resolutions. One method is the expansion of the cycle on which logical slowdown/speedup is performed in order to achieve a finer adjustment resolution. As shown in
FIG. 2
, a signal from an oscillation circuit
201
is subjected to frequency division by a frequency division circuit
202
, and a logical slowdown/speedup circuit
205
is operated on cycles counted by a first slowdown/speedup cycle counter
203
to perform a slowdown/speedup operation according to data fetched through a slowdown/speedup data input port
207
and stored in a slowdown/speedup data storing circuit
206
. For example, when a logical slowdown/speedup operation is performed on a cycle of 320 seconds, adjustment is possible at an adjustment resolution of 1/32768×86400/320=8 msec./day, and a sufficient resolution is thus obtained to provide a highly accurate electronic timepiece.
However, an expansion of a logical slowdown/speedup cycle results in a demerit in that the adjustable range is narrowed, although a finer adjustment resolution is achieved. Therefore, a logical slowdown/speedup operation has been performed also on a shorter cycle provided by a second slowdown/speedup cycle counter
204
to achieve a finer adjustment resolution and a wider adjustable range by combining logical slowdown/speedup operations on shorter and longer cycles.
However, for a conventional high accuracy electronic timepiece, a custom IC for the high accuracy electronic timepiece has been: developed after determining the operational cycle of the logical slowdown/speedup circuit and the number of bits of the slowdown/speedup data input port in advance. As a result, the minimum resolution and adjustable range of the logical slowdown/speedup circuit have been fixed, and actual factory adjustment of accuracy has faced a problem in that the yield of mass production has been significantly affected by inability to achieve target accuracy due to variation of adjusting accuracy from factory to factory and depending on the temperature, environment and the like. Further, an increase in cost can result from screening of quartz and the like when the frequency of the quartz used in oscillation circuits varies beyond the adjusting range fixed by the ICs. Further, while some ICs for high accuracy electronic timepieces include a correction means for after services provided when accuracy is deteriorated with time due to the aging properties of quartz and the like, a problem still arises in that re-adjustment can not be performed because the amount of adjustment allotted to the ICs at the time of the development of the same allows a slowdown/speedup amount that is too coarse or too fine for re-adjustment at retail shops and the like. These problems are found only after ICs are developed and products are released to factories and market and lead to various problems including a reduction of yield, cost increase and late deliveries associated with modifications of IC hardware.
SUMMARY OF THE INVENTION
The present invention first provides an electronic timepiece comprising an oscillation circuit, a system clock generation circuit for generating a system clock based on the output of the oscillation circuit, a frequency division circuit for performing frequency division on the output of the oscillation circuit, a ROM in which processing procedures such as a time-measuring operation of the clock are programmed, a CPU for interpreting the data programmed in the ROM to perform various arithmetic processes, a RAM for storing various data, an interrupt signal generation circuit for generating an interrupt signal to the CPU, a slowdown/speedup data input port for taking in slowdown/speedup data from the outside, a logical slowdown/speedup circuit for varying the frequency division ratio of the frequency division circuit to adjust accuracy, and a slowdown/speedup data storing circuit for storing slowdown/speedup data that determine the amount of slowdown/speedup at the logical slowdown/speedup circuit.
Second, there is provided a configuration which is the first configuration added with a slowdown/speedup correction data input port for taking in data from the outside for correcting the slowdown/speedup data input through the slowdown/speedup data input port.


REFERENCES:
patent: 4142360 (1979-03-01), Akahane
patent: 4427302 (1984-01-01), Watanabe
patent: 5717661 (1998-02-01), Poulson

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