Electronic circuit that comprises a memory matrix and method...

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S206000, C365S207000, C365S185200

Reexamination Certificate

active

07952949

ABSTRACT:
Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).

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patent: 6462998 (2002-10-01), Proebsting
patent: 6639846 (2003-10-01), Nikutta
patent: 10116325 (2002-10-01), None
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Gulati K et al; “Single Event Mirroring and DRAM Sense Amplifier Designs for Improved Single-Event Upset Performance”. IEEE Transactions on Nuclear Science, vol. 41, No. 6, pp. 2026-2034, Dec. 1994. IEEE, Piscataway, NJ, USA.
Zaid Al-Ars et al, “Effects of Bitline coupling on the faulty Behaviour of DRAMs”, IEEE VLSI test symposium, 2004, see whole document [20040101AlArsZaid].
J.S. Yuan et al, “Parasitic Effects on the Multilevel Interconnects in DRAM Circuits”, IEEE, 1990, see whole document [19900101YuanJS].

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