Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2006-05-18
2011-12-27
Barnie, Rexford (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
08085518
ABSTRACT:
An electronic circuit and method for producing the electronic circuit, where the electronic circuit includes a functional circuit including at least one multigate functional field effect transistor and an ESD protection circuit including at least one multigate ESD protection field effect transistor. The multigate protection field effect transistor is a transistor that is partially depleted of electrical charge carriers, and the trigger voltage of the multigate protection field effect transistor is less than the trigger voltage of the multigate functional field effect transistor.
REFERENCES:
patent: 5274262 (1993-12-01), Avery
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5773864 (1998-06-01), Merrill
patent: 6021071 (2000-02-01), Otsuka
patent: 6034552 (2000-03-01), Chang et al.
patent: 6100565 (2000-08-01), Ueda
patent: 6242763 (2001-06-01), Chen et al.
patent: 6433609 (2002-08-01), Voldman
patent: 6587320 (2003-07-01), Russ et al.
patent: 6642088 (2003-11-01), Yu
patent: 6720619 (2004-04-01), Chen et al.
patent: 6750515 (2004-06-01), Ker et al.
patent: 7224560 (2007-05-01), May et al.
patent: 7268398 (2007-09-01), Vashchenko et al.
patent: 2003/0184933 (2003-10-01), Lin et al.
patent: 2004/0041215 (2004-03-01), Chaine et al.
patent: 2004/0090806 (2004-05-01), Yoshida et al.
patent: 2004/0188705 (2004-09-01), Yeo et al.
patent: 2006/0114629 (2006-06-01), Wu et al.
patent: 2006/0214226 (2006-09-01), Chen et al.
patent: 0 939 439 (1999-09-01), None
patent: WO 2004/051749 (2004-06-01), None
M.G. Khazhinsky et al., “Engineering Single NMOS and PMOS Output Buffers for Maximum Failure Voltage in Advanced CMOS Technologies”, 2004 EOS/ESD Symposium.
P. Raha et al., “Reliability of Partially Depleted SOI Technology”, In: IEEE Transactions on Electron Devices, vol. 46, No. 2, Feb. 1999, Seiten 429 bis 431.
Hari Anathan, “FinFET—Current Research Issues”, School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET”, IEEE Transactions on Elctron Devices, vol. 48, No. 5, May 2001.
W. Xiong et al., “Full/partial depletion effects in FinFETs”, Electronics Letters, Apr. 14, 2005, vol. 41, No. 8.
S. Okhonin et al., “FinFET based Zero-capacitor DRAM (Z-RAM) Cell for sub 45 nm Memory Generations”, ICMTD-2005.
Office Communication from Search Report from German Patent and Trademark Office, Dated Dec. 13, 2006, pp. 1-5.
Ming-Dou Ker et al., Investigation on ESD Robustness of CMOS Devices in a 1.8-V 0.15-μm Partially-Depleted SOI Salicide CMOS Technology, Integrated Circuits & Systems Laboratory, Institute of Electronics, National Chiao-Tung Universtiy, Hsinchu, Taiwan, pp. 41 & 43 (With respect to Non-Patent Literature Document B2, we are submitting pp. 41 & 43, additional pages will be supplied as soon as they are received.).
Ming-Dou Ker et al., Investigation on ESD Robustness of CMOS Devices in a 1.8-V 0.15μm Partially-Depleted SOI Salicide CMOS Technology, Integrated Circuits & Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, pp. 41-44.
Chaudhary Nirmal
Russ Christian
Schulz Thomas
Barnie Rexford
Hoang Ann
Infineon - Technologies AG
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