Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-07
2004-04-13
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06721930
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the reduction of crosstalk in an electronic circuit device or system such as semiconductor integrated circuit (LSI), circuit mounted in a package, and an electronic circuit device mounted on a printed circuit board. In particular, the present invention relates to the application in electronic logic circuit system such as general-purpose processor, signal processor, ASIC, gate array, FPGA, image processor, semiconductor memory, system module, memory module, computer system, portable device system, etc.
2. Description of the Related Art
In the past, a logic circuit has been manufactured as follows: A large or a small circuit having a certain logic functions and called a cell or a block is disposed in a package or on a semiconductor integrated circuit chip or on a printed circuit board. Then, input/output terminals of each cell or circuit block are connected using metal wires. If the semiconductor integrated circuit chip (the components such as ASIC, gate array, FPGA, etc.), package module, or system on substrate can be fabricated within small area, it would be advantageous from economical viewpoint. Therefore, it is desirable that integration density or mounting density of cells, blocks and wires can be made as high as possible.
For this reason, in the field of semiconductor integrated circuit, fabrication technique has been increasingly miniaturized. The mounting technique in package or on substrate has been turned to higher density. However, when it is tried to accommodate a great number of elements and wires within a small region, various problems arise. One of these problems is the problem of crosstalk.
Crosstalk means interference of signals, which may occur between wires when a plurality of wires are arranged at positions physically closer to each other. In general, the functions to be processed by circuit are designed in such manner that the processing can be completed within a given delay time and integrated circuit and system can be operated at a desired frequency. In this case, if design is performed without taking the crosstalk into account, the change of delay time caused under the influence of signal interference is often overlooked. Under such circumstances, semiconductor integrated circuit chip or system may not be operated at the desired frequency.
If semiconductor integrated circuit chip or system is not operated at the desired frequency, the chip or the system must be re-designed, and this means a great loss of cost and time. To avoid such situation, it is necessary to avoid or reduce the problem of delay time degradation due to crosstalk after accurately analyzing degradation of delay time due to crosstalk.
The difficulty in the problem of delay time degradation due to crosstalk is the fact that its influence changes depending on signal arrival time. This is described in the article presented by the present inventors: “Crosstalk Delay Analysis using Relative Window Method”; Proceedings of IEEE International ASIC/SOC Conference 1999, pp. 9-13 (hereinafter referred as the reference 1).
Specifically, delay time is subject to diverse changes (degradation) depending upon the timing of signal arrival time (victim signal arrival time; VSAT) on the wire, for which analysis of delay time is to be performed (hereinafter referred as “the wire in question” or “victim”) and signal arrival time (aggressor signal arrival time; ASAT) on the wire, which interferes the above wire (hereinafter referred as “the adjacent wire” or “aggressor”) (Hereinafter, the value of this change is referred as “delay time degradation value”).
FIG. 1
is used to explain an example of delay degradation, which depends upon a combination of signal arrival time of victim and aggressor. A circuit diagram is shown on left side, and a delay degradation characteristic table corresponding to the circuit is given on right side.
In the cited reference 1, relative signal arrival time (RSAT), which is obtained by relatively measuring ASAT using VSAT as a reference, is used to address this problem. In this case, as in
FIG. 2
, which shows the change of delay degradation value due to relative signal arrival time (RSAT), the delay time degradation values are represented on a graph or a table with the relative signal arrival time on axis of abscissa. This is prepared in advance for a combination of drivers, which drive victim and aggressor. For each actual case, this graph or the table is drawn, and delay time degradation values are calculated.
Further, another difficulty relating to this problem lies in that VSAT or ASAT themselves may change according to the input patterns.
FIG. 3
shows this fact. An example of circuit diagram is shown on left side, and a characteristic table is given on right side based on the measurement of the changes of signal arrival time depending on the input patterns (signal paths) to correspond to the circuit. For instance, in case there is a change in a given input pattern, signal is transmitted from in
1
to n
2
via n
1
. In this case, the signal arrival time at the node n
2
is 0.40 ns. However, in another input pattern change, signal is transmitted from in
3
to n
2
, and signal arrival time at the node n
2
is 0.10 ns, and this is different from the above value. For this reason, it is not possible to uniquely determine RSAT, and the degradation table of
FIG. 2
cannot be applied in simple manner.
In the reference 1, this problem is addressed by utilizing a concept called “relative window”.
FIGS. 4A
to
4
C show this method. VSAT and ASAT are changed according to the input pattern, and these cannot be obtained as a time at a certain node. Therefore, VSAT or ASAT is calculated as a window with a certain width (FIG.
4
A: VSAT and ASAT window calculation). Next, RSAT cannot be uniquely determined, and it is calculated as a window having a width (hereinafter referred as “relative window”) (FIG.
4
B: relative window calculation). Here, the relative window is a range from the time when RSAT is at minimum to the time when it is at maximum. The time when RSAT is at minimum is the time when ASAT is at minimum and VSAT is at maximum. On the other hand, the time when RSAT is at maximum is the time when ASAT is at maximum and VSAT is at minimum. Finally, the worst value is obtained in the range of the relative window using the relative window and the degradation table already prepared, and the quantitatively determined delay time degradation value can be obtained (FIG.
4
C: acquisition of delay degradation value).
A more detailed analysis method in case there are a plurality of adjacent wires is described by the present inventors in: “Multi-aggressor Relative Window Method”; Proceedings of IEEE Custom Integrated Circuits Conference 2000, pp. 495-498 (hereinafter referred as the reference 2).
In the meantime, with the purpose of avoiding and reducing delay time degradation due to crosstalk, it is necessary to achieve such reduction by accurately calculating and evaluating the influence of the signal arrival time as described above. The reference 1 gives an example. Delay gate is inserted to a bus, where the signal arrives earlier when the signal arrival time at the gate output for driving the wire in question has a greater width, and signal arrival time for each bus is equalized. The signal arrival time at the wire in question is narrowed down and is separated from the signal arrival time of the adjacent wire in order to reduce crosstalk. In another example, when signal arrival time of two wires located on adjacent tracks is closer to each other, one of the wires is replaced with the wire on the other track, and signal arrival time is separated in order to reduce crosstalk. JP-A-11-40677 (hereinafter referred as the reference 3) describes a method to insert delay gate and to eliminate crosstalk error when there is timing overlap in signal arrival time.
As described above, when a circuit is realized within narrow space, wires are arranged at positions closer to each other, and there arises a proble
Kato Naoki
Sasaki Yasuhiko
A. Marquez, Esq. Juan Carlos
Bowers Brandon
Fisher Esq. Stanley P.
Reed Smith LLP
Siek Vuthe
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