Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-18
2002-12-31
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06502232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to electronic circuit design verification and validation in a computer environment. More particularly, the invention relates to constraining test simulator input signals to a design under verification to the ranges encountered in the design's normal operating environment.
2. Description of the Prior Art
Functional verification is concerned with ensuring that an electronic circuit design implements the intended functional behavior. Functional verification is commonly performed by applying deterministic or pseudo-random tests to a simulation model of the circuit design and analyzing its behavior.
A test generation engine takes a design and a set of test goals as input and produces tests, which are sequences of input vectors, that fulfill the test goals. A typical goal is to exercise all state transitions of a finite-state machine embedded in the circuit design.
Unconstrained test generation methods assume that the primary inputs to the circuit design under verification (DUV) can be driven independently of each other. The problem with these methods is that they may produce tests that are not meaningful because they fall outside the intended operating conditions for which the DUV was designed. A large numbers of tests are generated and a pass/fail outcome is computed for each test by simulating the design for each test. The user may have to sort through each failure, through manual or automatic means, to determine if the conditions leading to the failure are possible in the intended environment.
The circuit design, in its normal operating environment, is only going to be exercised for a certain set of legal behaviors. The legal behaviors are not defined by the circuit design itself, but rather the environment. In existing approaches, the circuit design parameters are used by the test generator and the environmental constraints are not taken into account. The test generator will then create tests that span the universe of behaviors. The challenge is to integrate the environmental constraints into test generation.
It would be advantageous to provide an electronic circuit design environmentally constrained test generation system that automatically constrains the test inputs to a DUV to the environmental constraints of the DUV's intended operating environment. It would further be advantageous to provide an electronic circuit design environmentally constrained test generation system that produces test results that are meaningful within the realistic operating parameters of the DUV.
SUMMARY OF THE INVENTION
The invention provides an electronic circuit design environmentally constrained test generation system. The system automatically constrains the test inputs to a design under verification (DUV) to the environmental constraints of the DUV's intended operating environment. In addition, the invention provides test results that are meaningful within the realistic operating parameters of the DUV.
A preferred embodiment of the invention provides a corrector mechanism that filters the input signals to the DUV. The corrector ensures that inputs signals to the DUV are within the given environmental constraints. Both combinational and temporal constraints can be handled by the corrector.
The corrector consists of a new element, a mapper, and an observer. The mapper looks at the observer's state and input value and changes the input to the DUV to place the DUV in a legal state if the input would place it on a track to an illegal state. The inputs are constrained to the normal expected operating environment of the DUV. The mapper is created by a compiler that takes into account the device's intended environment and the device's states.
The compiler creates the mapper by taking a description of the environmental constraints, and optionally a description of the DUV, and creates an abstract description of a finite state machine. A state graph is computed from the finite state machine. From the state graph, a set of states is analyzed where the states are found from which an illegal state is unavoidable. The mapper is created using these states. The set of inputs are fed to the DUV by the mapper. A feedback loop from the DUV to the observer may be implemented if the constraints rely. upon the DUV's state.
REFERENCES:
patent: 6269467 (2001-07-01), Chang et al.
patent: 6324678 (2001-11-01), Dangelo et al.
K.D. Jones, an J.P. Privitera; The Automatic Generation of Functional Test Vectors for Rambus Designs; 33rdDesign Automation Conference; 1996.
Jun Yuan, Kurt Shultz, Hillel Miler, Adnan Aziz; Modeling Design Constraints and Biasing in Simulation Using BDDs; 1999 IEEE.
Glenn Michael A.
Lee Wilson
Verisity Design, Inc.
Wong Don
WOng Kirk D.
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