Electronic chip package with reduced contact pad pitch

Details Electronic chip package with reduced contact pad pitch Electronic chip package with reduced contact pad pitch

2011-06-21

2011-06-21

Dang, Phuc T (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Die bond

C257S690000, C257SE23023, C438S106000, C438S612000

Reexamination Certificate

active

07964974

ABSTRACT:
An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.

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