Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – By pressure alone
Reexamination Certificate
2005-11-29
2005-11-29
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
By pressure alone
C257S783000, C257S786000, C257S782000, C257S778000
Reexamination Certificate
active
06969917
ABSTRACT:
The invention relates to an electronic chip component and a method for fabricating the chip component with a semiconductor chip having an integrated circuit therein. Contact surfaces are on the active surface of the semiconductor chip. The contact surfaces of the integrated circuit have a contact layer consisting of pressure contact material, which protrudes beyond the level of the top non-conductive layer. The active surface of the semiconductor chip includes a meltable glue layer that is adapted to the height of the contact layer.
REFERENCES:
patent: 5118370 (1992-06-01), Ozawa
patent: 5517752 (1996-05-01), Sakata et al.
patent: 5579573 (1996-12-01), Baker et al.
patent: 5635764 (1997-06-01), Fujikawa et al.
patent: 5925936 (1999-07-01), Yamaji
patent: 6002163 (1999-12-01), Wojnarowski
patent: 6063647 (2000-05-01), Chen et al.
patent: 6462284 (2002-10-01), Hashimoto
patent: 6710454 (2004-03-01), Boon
patent: 6774493 (2004-08-01), Capote et al.
patent: 2003/0222295 (2003-12-01), Lin
patent: 40 08 624 (1990-10-01), None
patent: 195 29 490 (1997-02-01), None
patent: 01-198017 (1989-08-01), None
patent: 02268451 (1990-11-01), None
patent: 05041407 (1993-02-01), None
patent: 05-291351 (1993-11-01), None
patent: 07-263474 (1995-10-01), None
patent: 08-045918 (1996-02-01), None
patent: 09-330932 (1997-12-01), None
patent: 11274241 (1999-10-01), None
patent: 2000031203 (2000-01-01), None
patent: 2000-150705 (2000-05-01), None
patent: 2000-164639 (2000-06-01), None
patent: 2004-504723 (2004-02-01), None
patent: WO 96/13066 (1996-05-01), None
patent: WO 99/56312 (1999-11-01), None
Johnson, C. D. et al.: “Wafer Scale Packaging Based on Underfill Applied at the Wafer Level for Low-Cost Flip Chip Processing”, IEEE Eletronic Components and Technology Conference, Jun. 1, 1999, pp. 950-954.
Erickson, C.: “Wafer Bumping: The Missing Link for DCA”, Electronic Packaging & Production, vol. 38, No. 8, Jul. 1, 1998, pp. 43-44 and 46.
Hacke Hans-Jürgen
Wossler Manfred
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Mandala Jr. Victor A.
Stemer Werner H.
LandOfFree
Electronic chip component with an integrated circuit and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electronic chip component with an integrated circuit and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic chip component with an integrated circuit and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3501568