Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-10-08
2010-12-07
Richards, N Drew (Department: 2895)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S316000, C257SE29309, C257SE21423, C365S185260
Reexamination Certificate
active
07847341
ABSTRACT:
Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.
REFERENCES:
patent: 5043940 (1991-08-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5434825 (1995-07-01), Harari
patent: 5583812 (1996-12-01), Harari
patent: 5714766 (1998-02-01), Chen et al.
patent: 5719808 (1998-02-01), Harari et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5937295 (1999-08-01), Chen et al.
patent: 5959896 (1999-09-01), Forbes
patent: 5991517 (1999-11-01), Harari et al.
patent: 6054349 (2000-04-01), Nakajima et al.
patent: 6060895 (2000-05-01), Soh et al.
patent: 6090666 (2000-07-01), Ueda et al.
patent: 6139626 (2000-10-01), Norris et al.
patent: 6159620 (2000-12-01), Heath et al.
patent: 6207229 (2001-03-01), Bawendi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6232643 (2001-05-01), Forbes et al.
patent: 6275419 (2001-08-01), Guterman et al.
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6317363 (2001-11-01), Guterman et al.
patent: 6317364 (2001-11-01), Guterman et al.
patent: 6319775 (2001-11-01), Halliyal et al.
patent: 6322901 (2001-11-01), Bawendi et al.
patent: 6333214 (2001-12-01), Kim et al.
patent: 6344403 (2002-02-01), Madhukar et al.
patent: 6407435 (2002-06-01), Ma et al.
patent: 6413819 (2002-07-01), Zafar et al.
patent: 6441392 (2002-08-01), Gautier et al.
patent: 6542956 (2003-04-01), Lee et al.
patent: 6559014 (2003-05-01), Jeon
patent: 6562491 (2003-05-01), Jeon
patent: 6576291 (2003-06-01), Bawendi et al.
patent: 6577532 (2003-06-01), Chevallier
patent: 6586349 (2003-07-01), Jeon et al.
patent: 6586785 (2003-07-01), Flagan et al.
patent: 6602805 (2003-08-01), Chang
patent: 6642573 (2003-11-01), Halliyal et al.
patent: 6656792 (2003-12-01), Choi et al.
patent: 6657253 (2003-12-01), Kim et al.
patent: 6670670 (2003-12-01), Chae et al.
patent: 6713846 (2004-03-01), Senzaki
patent: 6717226 (2004-04-01), Hegde et al.
patent: 6723606 (2004-04-01), Flagan et al.
patent: 6730537 (2004-05-01), Hutchison et al.
patent: 6750066 (2004-06-01), Cheung et al.
patent: 6753224 (2004-06-01), Lin et al.
patent: 6753570 (2004-06-01), Tripsas et al.
patent: 6781166 (2004-08-01), Lieber et al.
patent: 6803272 (2004-10-01), Halliyal et al.
patent: 6844604 (2005-01-01), Lee et al.
patent: 6872645 (2005-03-01), Duan et al.
patent: 6888739 (2005-05-01), Forbes
patent: 6949793 (2005-09-01), Choi et al.
patent: 6951782 (2005-10-01), Ding
patent: 6996009 (2006-02-01), Forbes
patent: 7005697 (2006-02-01), Batra et al.
patent: 7045851 (2006-05-01), Black et al.
patent: 7091120 (2006-08-01), Buretea et al.
patent: 7091548 (2006-08-01), Jeong et al.
patent: 7129554 (2006-10-01), Lieber et al.
patent: 7138680 (2006-11-01), Li et al.
patent: 7154140 (2006-12-01), Forbes
patent: 7169674 (2007-01-01), Bojarczuk, Jr. et al.
patent: 7217643 (2007-05-01), Liang et al.
patent: 7221586 (2007-05-01), Forbes et al.
patent: 7365389 (2008-04-01), Jeon et al.
patent: 7423326 (2008-09-01), Rotondaro et al.
patent: 2002/0130311 (2002-09-01), Lieber et al.
patent: 2003/0077625 (2003-04-01), Hutchinson
patent: 2003/0153151 (2003-08-01), Choi et al.
patent: 2004/0074565 (2004-04-01), Hayakawa et al.
patent: 2004/0130941 (2004-07-01), Kan et al.
patent: 2004/0144972 (2004-07-01), Dai et al.
patent: 2004/0266126 (2004-12-01), Lee
patent: 2005/0006696 (2005-01-01), Noguchi et al.
patent: 2005/0072989 (2005-04-01), Bawendi et al.
patent: 2005/0074982 (2005-04-01), Lee et al.
patent: 2005/0093054 (2005-05-01), Jung
patent: 2005/0148127 (2005-07-01), Jung et al.
patent: 2005/0181619 (2005-08-01), Hwu et al.
patent: 2005/0201149 (2005-09-01), Duan et al.
patent: 2005/0201150 (2005-09-01), Wang
patent: 2005/0202615 (2005-09-01), Duan et al.
patent: 2005/0236678 (2005-10-01), Sato et al.
patent: 2006/0001053 (2006-01-01), Wang
patent: 2006/0040103 (2006-02-01), Whiteford et al.
patent: 2006/0054943 (2006-03-01), Li et al.
patent: 2006/0081911 (2006-04-01), Batra et al.
patent: 2006/0166452 (2006-07-01), Rao et al.
patent: 2006/0175653 (2006-08-01), Joo et al.
patent: 2006/0175656 (2006-08-01), Govoreanu et al.
patent: 2006/0180851 (2006-08-01), Lee et al.
patent: 2006/0186457 (2006-08-01), Burnett et al.
patent: 2006/0231889 (2006-10-01), Chen et al.
patent: 2007/0018342 (2007-01-01), Sandhu et al.
patent: 2007/0032091 (2007-02-01), Heald et al.
patent: 2007/0045718 (2007-03-01), Bhattacharyya
patent: 2007/0056925 (2007-03-01), Liu et al.
patent: 2007/0096202 (2007-05-01), Kang et al.
patent: 2007/0122946 (2007-05-01), Hieda
patent: 2008/0150009 (2008-06-01), Chen
patent: 1324378 (2003-07-01), None
patent: WO-2006112793 (2006-10-01), None
patent: WO 2008/079684 (2008-07-01), None
patent: WO 2008/079684 (2008-07-01), None
Saitoh et al. In “1.2 nm HfSiON/SiON Stacked Gate Insulators for 65-nm-Node MISFETs”, 2005, Japanese Journal of Applied Physics, vol. 44, No. 4B, pp. 2330-2335.
Specht et al. In “Charge trapping memory structures with A12O3 trapping dielectric for high-temperature applications”, 2005, Solid-State Electroncis 49, pp. 716-720.
Aminzadeh, M. et al. “Conduction and charge trapping in polysilicon-silicon nitride-oxide-silicon structures under positive gate bias,” IEEE Trans Elec. Dev. (1988) 35:459-467.
Atwater, H.A. “Silicon nanoparticle engineering for novel logic and memory applications,” Project Overview, Functional Nanostructures Program, NSF (Jan. 2001).
International Search Report for International Application No. PCT/US2007/87167 dated May 23, 2008.
The International Search Report and the Written Opinion of the International Searching Authority dated Nov. 20, 2009 for International Patent Application No. PCT/US2009/058182.
Pfeiffer, O.; Ayre, A. “Using Flash Memory in Embedded Applications,”Embedded Systems Academy, www.esacademy.com/faq/docs/flash/lifetime.htm, printed 2009, (2 pages).
Gutt, J.; Brown, G.A.; Senzaki, Y.; Park, S. “An Advanced High-k Transistor Utilizing Metal-Organic Precursors in an ALD Deposition of Hafnium Oxide and Hafnium Silicate with Ozone as Oxidizer,”Materials Research Society Symposium Proceedings, 2004, Materials Research Society, 811, D2.4.1-D2.4.6.
Kil, D-S.; Hong, K.; Lee, K-J.; Kim, J.; Song, H-S.; Park, K-S.; Roh, J-S.; Sohn, H-C.; Kim J-W; Park, S-W. “Development of Highly Robust Nano-mixed HfxAlyOz Dielectrics for TiN/HfxAlyOz/TiN Capacitor Applicable to 65nm Generation DRAMs,”Symposium on VLSI Technology Digest of Technical Papers, 2004, 126-127.
Liu, X.; Ramanathan, S.; Longdergan, A.; Srivastava, A.; Lee, E.; Seidel, T.E.; Barton, J.T.; Pang, D.; Gordon, R.G. “ALD of Hafnium Oxide Thin Films from Tetrakis(ethylmethylamino)hafnium and Ozone,”Journal of the Electrochemical Society, 2005, 152, G213-G219.
Suzuki, I.; Yanagita, K.; Dussarrat, C. “Extra Low-Temperature SiO2Deposition Using Aminosilanes,”210thECS Meeting, 2006, Abstract #1053.
Swerts, J.; Deweerd, W.; Wang, C-G.; Fedorenko, Y.; Delabie, A.; Shero, E.; Zhao, C.; Maes, J.W.; De Gendt, S.; Wilk, G. “Highly Scalable ALD-deposited Hafnium Silicate Gate Stacks for Low Standby Power Applications,”Materials Research Symposium Proceedings, 2006, 917, 6 pages.
Bell, L.D. et al., “A Radiation-tolerant, low-power non-volatile memory based on silicon nanocrystal quantum dots,” Forum on Innovative Approaches to Outer Planetary Exploration 2001-2020, Houston, TX, (2001).
Bez, R. et al. “Introduction to flash memory,” Proc. IEEE (2003) 91:489-502.
Bodefield, M.C
Chen Jian
Sharangpani Rahul
Brinks Hofer Gilson & Lione
Jung Michael
Nanosys Inc.
Richards N Drew
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