Electromigration risk analysis in integrated circuit power...

Details Electromigration risk analysis in integrated circuit power... Electromigration risk analysis in integrated circuit power...

2005-04-12

2005-04-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06880139

ABSTRACT:
Methods of and apparatuses for performing electromigration risk analyses of power interconnect systems in integrated circuits employ a pseudo dynamic simulation model, whereby all transistor gates of a transistor network coupled to the power interconnect system are switched at the same time. To accomplish simultaneity in switching, a netlist characterizing the transistor network is altered in a manner that all gates are connected to a common input signal node. Time dependent currents drawn by transistors of the transistor network connected to the power interconnect system are determined. The time dependent currents and dimensional characteristics gleaned from the layout of the integrated circuit are used to calculate peak, average, or RMS current densities. The current densities are compared to electromigration rules to determine what areas of the power interconnect system may be in violation of the electromigration rules.

REFERENCES:
patent: 5379231 (1995-01-01), Pillage et al.
patent: 6202191 (2001-03-01), Filippi et al.
patent: 6329866 (2001-12-01), Watarai
Liew et al., “Effects of High Current Pulses on Integrated Circuit Metallization Reliability”, IEEE, InterSociety Conference on Thermal Phenomena in the Fabrication and Operation of Electronic Components: I-Therm '88, pp. 3-6.

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