Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-09-29
2003-07-22
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C361S056000, C363S097000, C369S027010, C324S703000
Reexamination Certificate
active
06598182
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to systems for monitoring and controlling stress testing of electrical circuits and devices. More particularly, the invention relates to a test system for providing a stress to electrical devices such that the stress test can be automatically shut down before destructive failure of the device under test. The system monitors the stress levels of the parts of the circuit being tested to limit, among other parameters, the electromigration and extrusion occurring within the circuit during the stress testing. The limits are implemented automatically by localized electronics and thereby reduce the potential for overstressing and destruction of the circuit being tested. The system is particularly suited to monitoring and controlling a high-temperature, constant-current stress applied to a device.
BACKGROUND OF THE INVENTION
In qualifying a new electronics technology, it is helpful and often necessary to evaluate the reliability of the technology. More particularly, evaluation of the reliability of the electrical circuits or devices is important. One aspect of the reliability testing is to evaluate the electromigration and extrusion of the circuit or device under constant current conditions.
Although the testing of the circuit is important, it is also valuable to be able to physically analyze the structure of the circuit after the stress test to obtain an understanding of how the structure was altered as a result of the stress imposed. A problem with the testing and stressing of a circuit is the potential for overstressing the structure. When such overstressing occurs, and because of the speed at which such stresses affect the device, the structure is often destroyed, making analysis of the stress effects impossible. The destruction that occurs to a device after overstressing often occurs in very short time intervals, and thus human intervention is too slow to prevent destruction after the device reaches its stress limit.
Current techniques for testing and monitoring circuits use a computer-controlled scanner to read the status and condition of each part of the structure under stress. Typically, a constant current is applied to the structure and a voltage is applied to the extrusion monitor. As part of current testing techniques, preset limits are specified for the resistance being monitored in the structure, and the extrusion monitor current is not limited in any manner. When the computer observes, through the scanner, that the resistance of the structure has increased above the preset limit, or that the extrusion monitor has begun to draw current above the preset limit, a stop-stress-test signal is sent by the computer.
Inherent time delays are associated with a computer scanner as it senses limit states. Additional delays occur during the time the computer takes to respond to such conditions. Therefore, the stop-stress-test signal often occurs after the device under test has already been destroyed. As noted, the destruction of a device may occur at electronic speeds.
Moreover, the conventional hardware available and used for such qualification testing is often selected for use with sampling plans and factory statistical analyses. As part of sampling plans and factory statistical analyses, there is generally no need for testing the failure characteristics of a stressed device. Therefore, current stress and monitor equipment is not designed to react in the necessary time intervals to prevent destruction.
Accordingly, there remains a need for a stress and monitor system to allow stress testing of a device while monitoring the stress conditions of the device such that the testing can be stopped at electronic speeds before the device is destroyed. The stress and monitor system should be able to monitor multiple channels and have pre-selected limits for allowable stress. The system should also be capable of recording the condition and stress channel that caused the system to shut down the stress testing. With such a system, electrical devices may be qualified under stress and still be analyzed afterwards to determine how the structural mechanisms of the device under test are affected by the stress loading.
SUMMARY OF THE INVENTION
To overcome the shortcomings of the prior art, it is an object of the present invention to provide a stress and monitor system for electrically stressing an electrical device with the capability of turning the stress load off at electronic speeds such that the device under test is not destroyed. To achieve this and other objects, and in view of its purposes, the present invention provides an electrical stress and monitor system for electrically stressing an electrical device, comprising a plurality of stress channels for stressing the electrical device and a plurality of control and monitor circuits. Each of the circuits is paired with one of the plurality of stress channels, each of the circuits has a predefined limit stress level, and each of the circuits communicates with and controlling the plurality of stress channels so that, if a control and monitor circuit senses a stress level at the predefined limit stress level, the control and monitor circuit shuts down the paired stress channel.
It is a further object of the present invention to provide a high-temperature, constant-current stress and monitor system for electrically stressing an electrical circuit, comprising a plurality of stress channels; a plurality of control and monitor circuits, each of the circuits being paired with one of the plurality of stress channels and communicating with and controlling the plurality of stress channels such that, if a control and monitor circuit senses a limiting stress level, the control and monitor circuit shuts down the paired stress channel; a control bus communicating with each of the paired stress channels and control and monitor circuits; a status and enabling mechanism communicating with the paired stress channels and control and monitor circuits through the control bus, the status and enabling mechanism (1) determining the status of the stress channel, (2) controlling the stress input, and (3) enabling and disabling the control and monitor circuits; and a computer communicating with the status and enabling mechanism through a serial interface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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patent: 6118639 (2000-09-01), Goldstein
Lowitz Nicholas J.
Montrose Charles J.
Beausoliel Robert
International Business Machines - Corporation
RatnerPrestia
Townsend, Esq. Tiffany L.
Ziemer Rita A
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