Electromagnetically coupled fail-safe logic circuit

Details Electromagnetically coupled fail-safe logic circuit Electromagnetically coupled fail-safe logic circuit

1994-03-16

1995-08-15

Hudspeth, David R.

Electronic digital logic circuitry

Reliability

Fail-safe

326 31, 257531, H03K 19003

Patent

active

054423031

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to an electromagnetically coupled fail-safe logic circuit that is integrated (compact) and capable of providing a low-potential output.


BACKGROUND ART

An example of a fail-safe logic circuit is disclosed in "Fail-Safe Scan Circuit" (PCT/JP92/00631) proposed by the present inventors.
This circuit employs a plurality of AC input signals each representing a binary value, i.e., a logic value of 1 (with an output) or 0 (with no output). The signals never take the logic value 1 by error when failure occurs. The levels of these AC input signals are rectified, added up, and converted into a multilevel signal according to the number of the input signals by an adder. The adder employs a voltage doubler rectifier that includes a coupling capacitor, a clamp diode, a rectifier diode, and a smoothing capacitor. The level of the multilevel signal is tested by a fail-safe threshold operation element such as a fail-safe window comparator of which output signal is zero (corresponding to the logic value 0) when failure occurs. The threshold operation element provides a binary output signal representing the logic value 0 or 1 based on the level result.
The sum of a plurality of binary input signals Pi (i=1 to n) is expressed as P1+P2+ . . . +Pn. The logical product and logical sum operations of these input signals are expressed as follows with an operation output of h: ##EQU1##
When calculating the logical product of the binary signals P.sub.i, the threshold of the threshold operation element must be set to provide the output h of 1 if each of the input signals P.sub.i indicates the logic value 1. When calculating the logical sum of the signals, the threshold of the threshold operation element must be set to provide h=1 if any one of the input signals P.sub.i indicates the logic value 1.
This fail-safe logic circuit has the following three characteristics:
Firstly, the same circuit is applicable to calculating logical product and logical sum because the circuit is programmable to select any one of the logical operations according to the setting of the threshold. Secondly, a logic value representing the sum P1+P2 . . . +Pn of the binary input signal P.sub.i errs in the direction of decrease, further, the threshold operation element never provides an output representing the logic value 1 even if failure such as short circuit or disconnection occurs in one of the capacitors and diodes in the voltage doubler rectifier. Accordingly, the circuit never erroneously provides an output representing the logic value 1 even if there is no input signal Pi. Thirdly, the circuit calculates the sum of the input signals Pi each never erring to the logic value 1, converts the sum into a multilevel value that never errs to increases, and carries out the threshold operation that never errs to the logic value 1, to provide a binary signal. Due to these characteristics, a plurality of the logic circuits may be connected in cascade to carry out fail-safe logic operations.
In this logic circuit, the level of a binary input signal representing the logic value 1 is actually provided by power source potential Vcc. Accordingly, if the coupling capacitor causes a short-circuit failure, there will be a risk of transmitting the power source potential Vcc to the output side even if the signals do not represent the logic value 1. To secure the fail-safe property of the logic circuit, it is necessary to employ the clamp diode to make the minimum potential of the sum P1+P2+ . . . +Pn of the input signals equal to the power source potential Vcc. (This technique is called the power source outside process.) This power source outside process is troublesome and complicates the circuit. In addition, the clamping may increase the potential of the summed output.
The logic circuit mentioned above accumulates the outputs of the binary input signals as charges in the capacitors and adds them up. Accordingly, there is a limit on minimizing (integrating) the logic circuit.
The present inventors have proposed a very small tra

REFERENCES:
patent: 3423728 (1969-01-01), Wissel
patent: 3819933 (1974-06-01), Grundy
patent: 3913023 (1975-10-01), Dolch
patent: 3953747 (1976-04-01), Sekiguchi
patent: 3992636 (1976-11-01), Kiffmeyer
patent: 4130764 (1978-12-01), Darrow
patent: 4587077 (1986-05-01), Bessedine
patent: 4661880 (1987-04-01), Futsuhara
patent: 4785345 (1988-11-01), Rawls et al.
patent: 5065047 (1991-11-01), Igari et al.

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