Electromagnetically-coupled bus system

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C333S109000, C333S124000, C333S238000, C333S246000, C375S257000, C375S258000

Reexamination Certificate

active

07080186

ABSTRACT:
The present invention provides a mechanism for supporting high digital bandwidth in a multi-drop bus system. A first device of the system is electrically coupled to a bus. Multiple receiving devices are coupled to the bus through associated electromagnetic couplers having coupling coefficients in a specified range. The geometries of the electromagnetic couplers are selected to reduce variations in the coupling coefficients with changes in the relative positions of the coupler components.

REFERENCES:
patent: 3516065 (1970-06-01), Bolt et al.
patent: 3619504 (1971-11-01), De Veer et al.
patent: 3764941 (1973-10-01), Nick
patent: 3786418 (1974-01-01), Nick
patent: 3835252 (1974-09-01), Ananiades et al.
patent: 4904879 (1990-02-01), Rudy, Jr. et al.
patent: 5365205 (1994-11-01), Wong
patent: 5629838 (1997-05-01), Knight et al.
patent: 5638402 (1997-06-01), Osaka et al.
patent: 6005895 (1999-12-01), Perino et al.
patent: 6016086 (2000-01-01), Williamson et al.
patent: 6111476 (2000-08-01), Williamson
patent: 6446152 (2002-09-01), Song et al.
patent: 6449308 (2002-09-01), Knight et al.
patent: 6493190 (2002-12-01), Coon
patent: 6496886 (2002-12-01), Osaka et al.
patent: 15 74 593 (1971-07-01), None
patent: 0 447 001 (1991-09-01), None
XTL Evaluation System Evaluation Memory Sub-System: Chip (HS-TEG: High Speed Test Engineering Group) and Dimm, Sep. 15, 2000, pp. 22-35, vol. SDL601-XTL-0-073 DMX 005 Systems Development Laboratory, Hitachi Ltd.
Hideki Osaka, High Performance Memory Interface from DDR-SDRAM II: XTL (Crosstalk Transfer Logic), Sep. 15, 2000, pp. 2-21, vol. SDL601-XTL-0-074 DMX 006.
Systems Development Laboratory, Hitachi Ltd., Ramin Farjad-Rad, et al. A 0.3-μm CMOS-Gb/s 4-PAM Serial Link Transeiver, May 5, 2000, pp. 757-764, IEEE Journal of Solid-State Circuits, vol. 35, No. 5.
Ken Yang et al., A 0.5-μm CMOS 4.0-Gbits/s Serial Link Transceiver with Data Recover Using Oversampling, May 5, 1998, pp. 713-722, IEEE Journal of Solid-State Circuits, vol. 33 No. 5.

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