Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2002-03-08
2004-10-26
Barlow, John E. (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C703S016000
Reexamination Certificate
active
06810340
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an EMS (Electromagnetic susceptibility) analysis method and EMS analysis apparatus and a method for manufacturing semiconductor devices using the EMS analysis apparatus, and in particular to a method for performing high-speed and high-accuracy EMS analysis on an LSI (Large-scale Integration) circuit featuring large-scale integration and high-speed driving to analyze direct EMS caused by electromagnetic radiation and indirect EMS caused by a power source.
As semiconductor integrated circuits have become faster and achieve larger packing densities, EMS (Electromagnetic susceptibility) has become a serious problem where semiconductor integrated circuits malfunction due to external noises.
One of the possible causes of EMS is that a noise external to a semiconductor integrated circuit entering a power line is propagated inside the semiconductor integrated circuit, affecting signal lines and functional elements, thus causing malfunction of the circuit. Conventionally, tests have been conducted in the design stage to simulate a noise in the signal line of a semiconductor integrated circuit by using a circuit simulator or a faster delay simulator and to check whether such a noise could cause malfunction of the circuit, in order to analyze malfunction caused by a noise entering the semiconductor integrated circuit.
Methods for analyzing a noise other than the EMS noise includes a method for analyzing a crosstalk noise between signal wires in an LSI circuit. As an example of such a method, a method is proposed for analyzing a noise propagated to the circuit elements of the victim caused by a variation in the signal output from the circuit elements of the aggressor due to a coupling capacitance between parallel signal lines thereby analyzing a noise between signal wires, as shown in
FIG. 35
(Japanese Patent Publication No. Hei. 6-243193). This technology does not consider the influence that occurs between a power line and a signal line so that it is impossible to analyze the EMS noise.
As shown in
FIG. 36
, it is possible to input a signal S containing a noise to a power source by using a transistor level simulator such as SPICE. However, in order to locate a disturbance leading to malfunction, it is necessary to perform a large number of test patterns, check the output signals at the circuit elements (gates) and conforming that values different from the expected ones are obtained.
That is, it is necessary to provide test probes for all the cells in order to locate the disturbance. This work is quite difficult in the case of an LSI circuit.
Even when the disturbance is located, which gate must be modified is unknown.
To accurately locate the disturbance, it is necessary to place the LSI circuit in the operating state while using a large number of test vectors.
The aforementioned related art requires huge simulation time for an LSI circuit. The technology considers the case where a noise is generated in a signal line due to a variation in a signal caused by circuit elements in the circuit, or a crosstalk noise, but not the case where a noise is generated in a power line, that is, the influence of indirect EMS on the interior of a semiconductor integrated circuit, or where a noise is generated inside a semiconductor integrated circuit caused by electromagnetic radiation, that is, direct EMS. It is difficult to analyze how the EMS affects a semiconductor integrated circuit and how a circuit is to be modified to cope with the EMS.
As the circuit scale becomes larger, the semiconductor integrated circuit is facing a serious problem of malfunction due to an external power noise (indirect EMS) or a radiation noise due to electromagnetic waves (direct EMS). Conventionally, a method has been employed for evaluating the resistance of a semiconductor integrated circuit to an external noise by providing the semiconductor integrated circuit with a power noise or external strong electromagnetic waves after the semiconductor integrated circuit is manufactured, in order to check the resistance of a semiconductor integrated circuit to an external noise. In case the semiconductor integrated circuit is less resistant to a noise, a de-coupling capacitor is inserted in the semiconductor integrated circuit or the circuit is modified to improve the resistance to a noise.
In this way, inspection on the resistance of a semiconductor integrated circuit to an external noise is performed after the circuit is manufactured. In case any problem occurs concerning an external noise during inspection, the entire semiconductor integrated circuit requires modification. This increases the design period.
SUMMARY OF THE INVENTION
The invention has been proposed in view of the foregoing situation and relates to a method for reducing electromagnetic wave disturbance while maintaining the high integration density and high-speed characteristics of an LSI circuit.
The invention aims at preventing malfunction caused by indirect EMS where an external noise enters the power source and malfunction caused by direct EMS caused by electromagnetic wave radiation as well as readily provide the layout of a reliable semiconductor integrated circuit device.
The invention aims at providing a method for readily identify the location in the design stage where circuit malfunction could be potentially caused by a noise, by obtaining the propagation of a noise waveform in a large-scale semiconductor integrated circuit.
Further, the invention aims at enhancing the resistance of a semiconductor integrated circuit to a noise before manufacturing the circuit by simulating the verification of circuit operation against a power noise.
In order to attain the foregoing object, a method for analyzing an external noise to a semiconductor integrated circuit according to the invention is characterized in that the method comprises an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.
According to such steps, an equivalent circuit is created from impedance information, a noise waveform is externally supplied to the equivalent circuit and the influence of the noise on the semiconductor integrated circuit is analyzed. It is thus possible to readily take high-accuracy EMS countermeasures.
The second aspect of the invention is characterized in that the analysis step includes a noise waveform supplying step of supplying a start point power noise waveform, a power noise waveform calculating step of obtaining power noise waveforms at the internal node points and terminals in the semiconductor integrated circuit, and an error section detecting step of obtaining the influence of an external noise on the semiconductor integrated circuit and detecting sections susceptible to an external noise entering the semiconductor integrated circuit.
With this configuration, it is possible to readily detect the sections susceptible to an external noise thus readily taking high-accuracy EMS countermeasures
The third aspect of the invention is characterized in that the equivalent circuit creating step comprises a functional block power equivalent circuit creating step of creating a degenerate impedance circuit of each functional block in a semiconductor integrated circuit from the impedance information and an inter-block power equivalent circuit creating step of creating a circuit for analyzing the inter-block power wiring in the semiconductor integrated circuit from the impedance information and that the analysis step uses as the equivalent circuit at least one of the degenerate impedance circuit and the circuit for analyzing the inter-block power wiring.
The fourth aspect of
Hirano Shouzou
Kurazono Ritsuko
Matsui Kaori
Shimazaki Kenji
Tsujikawa Hiroyuki
Barlow John E.
Matsushita Electric - Industrial Co., Ltd.
Taylor Victor J
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