Electrolysis: processes – compositions used therein – and methods – Electrolytic erosion of a workpiece for shape or surface...
Reexamination Certificate
2001-09-19
2004-10-26
Nicolas, Wesley A. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic erosion of a workpiece for shape or surface...
C205S641000, C205S644000, C205S645000, C205S646000, C205S220000, C205S222000, C205S223000, C205S229000, C205S316000
Reexamination Certificate
active
06808617
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application(s) No(s). P2000-284260 filed Sep. 19, 2000, which application(s) is/are incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a polishing method, a polishing apparatus, a plating method, and a plating apparatus used in producing a semiconductor device, more particularly relates to a polishing method and a polishing apparatus of a copper film or other film in a damascene process and a plating method and a plating apparatus used in processes of forming a copper film etc.
2. Description of the Related Art
Along with the increase in integration and reduction of size of semiconductor devices, progress has been made in miniaturization of interconnections, reduction of interconnection pitch, and superposition of interconnections. The importance of the multilayer interconnection technology in the manufacturing process of semiconductor devices is therefore rising.
On the other hand, conventionally aluminum has been frequently used as an interconnection material of a semiconductor device having a multilayer interconnection structure, but in order to suppress the propagation delay of signals in the recent 0.25 &mgr;m or less design rule, an interconnection process for replacing the aluminum of the interconnection material by copper is being developed. When using copper for interconnections, there is the merit that both a low resistance and a high electromigration tolerance can be obtained.
In a process using this copper for interconnections, for example, an interconnection process referred to as the damascene process for burying a metal in a groove-like interconnection pattern formed in an interlayer insulation film in advance and removing excess metal film by chemical mechanical polishing (CMP) to form the interconnections has become dominant. The damascene process has the characteristics that etching of the interconnections become unnecessary and also a further upper interlayer insulation film becomes flat by itself, so the process can be simplified.
Further, by the dual damascene process where not only grooves for the interconnections, but also the contact holes are formed as grooves in the interlayer insulation film and where the interconnections and the contact holes are simultaneously buried by the metal, a greater reduction of the interconnection steps becomes possible.
Here, an explanation will be made of an example of the process for forming copper interconnections by the dual damascene process by referring to the figures below.
First, as shown in
FIG. 34A
, for example, an interlayer insulation film
302
made of for example silicon oxide is formed by for example low pressure chemical vapor deposition (CVD) on a silicon or other semiconductor substrate
301
on which a not illustrated impurity diffusion region is appropriately formed.
Next, as shown in
FIG. 34B
, contact holes CH communicating with the impurity diffusion region of the semiconductor substrate
301
and grooves M in which will be formed a predetermined pattern of interconnections to be electrically connected to the impurity diffusion region of the substrate
301
are formed by using well-known photolithography and etching.
Next, as shown in
FIG. 34C
, a barrier metal film
305
is formed on the surface of the interlayer insulation film
302
and in the contact holes CH and the grooves M. This barrier metal film
305
is formed by a material such as Ta, Ti, TaN, or TiN by well-known sputtering. When the interconnection material is copper and the interlayer insulation film
302
is silicon oxide, since copper has a large diffusion coefficient with respect to silicon oxide, it is easily oxidized. The barrier metal film
305
is provided to prevent this.
Next, as shown in
FIG. 35A
, a seed film
306
is formed on the barrier metal film
305
to a predetermined thickness by well-known sputtering.
Then, as shown in
FIG. 35B
, a copper film
307
is grown and formed on the seed film
306
so as to bury the contact holes CH and the grooves M by copper. The copper film
307
is formed by for example plating, CVD, sputtering, etc.
Next, as shown in
FIG. 35C
, the excess copper film
307
and barrier metal film
305
on the interlayer insulation film
302
are removed by CMP for flattening.
Due to the above steps, copper interconnections
308
and contacts
309
are formed.
By repeating the above process on the interconnections
308
, multilayer interconnections can be formed.
Summarizing the problems to be solved by the invention, in the step of removing the excess copper film
307
by CMP in the copper interconnection forming process using the dual damascene process, because the flattening technique employing conventional CMP involves applying a predetermined pressure between a polishing tool and the copper film for polishing, there arises a problem that large damage is given to the semiconductor substrate.
Especially, in a case where an insulation film of a small dielectric constant, for example, a polyimide film or other organic insulation film, or an SiOF film comprised of silicon oxide including fluorine, or an inorganic insulation film such as porous silica or other gel insulation film, is used for the interlayer insulation film for the purpose of reducing the parasitic capacitance in interconnections to raise the operation speed of a semiconductor device, since generally these insulation films have low mechanical strength, the aforesaid damage in the above CMP process is no longer negligible and may cause cracks of the interlayer insulation film and separation of the interlayer insulation film from the semiconductor substrate.
Further, the removal performance differs among the interlayer insulation film
302
, the copper film
307
, and the barrier metal film
305
, therefore there has been the problem that dishing, erosion (thinning), recesses, etc. easily occur in the interconnections
308
.
Dishing is a phenomenon where, as shown in
FIG. 36
, when there is an interconnection
308
having a width of, for example, about 100 &mgr;m at a 0.18 &mgr;m design rule, the center portion of the interconnection is excessively removed and sinks. If this dishing occurs, the sectional area of the interconnection
308
becomes insufficient. This causes poor interconnection resistance etc. This dishing is apt to occur when copper or aluminum, which are relatively soft, is used as the interconnection material.
Erosion is a phenomenon where, as shown in
FIG. 37
, a portion having a high pattern density such as where interconnections with a width of 1.0 &mgr;m are formed at a density of 50% in a range of for example 3000 &mgr;m is excessively removed. When erosion occurs, the sectional area of the interconnections becomes insufficient. This causes poor interconnection resistance etc.
Recess is a phenomenon where, as shown in
FIG. 38
, the interconnection
308
becomes lower in level at the interface between the interlayer insulation film
302
and the interconnection
308
resulting in a step difference. In this case as well, the sectional area of the interconnection becomes insufficient, causing poor interconnection resistance etc.
Further, in the step of flattening and removing the excess copper film
307
by CMP, it is necessary to efficiently remove the copper film. The amount removed per unit time, that is, the polishing rate, is required to be for example more than 500 nm/min.
In order to obtain this polishing rate, it is necessary to increase the polishing pressure on the wafer. When the polishing pressure is raised, as shown in
FIG. 39
, a scratch SC and chemical damage CD are apt to occur in the interconnection surface. In particular, they easily occur in soft copper. For this reason, they cause opening of the interconnections, short-circuiting, poor interconnection resistance, and other defects. Further, if the polishing pressure is raised, there is the inconvenience that the amount of the scratches, separation of interlayer ins
Nogami Takeshi
Sato Shuzo
Segawa Yuji
Yoshio Akira
Depke Robert J.
Holland & Knight LLP
Nicolas Wesley A.
Sony Corporation
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