Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-11-27
2003-12-16
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S687000
Reexamination Certificate
active
06664122
ABSTRACT:
BACKGROUND
This invention relates to the formation of Damascene copper interconnects for integrated circuits. More specifically, the invention provides a procedure and conditions for deposition of a thin and relatively continuous electroless copper film on the surface of sub-micron integrated circuit features.
The Damascene process provides inlaid copper lines in dielectric layers of integrated circuits. The copper lines provide electrical routing between circuit elements in the integrated circuit. Damascene copper lines are rapidly replacing traditional aluminum etched lines in high-performance integrated circuitry.
In a Damascene process, both copper lines and vias are provided in horizontal layers of dielectric. A typical Damascene process begins by patterning an etch-resistant photoresist on a previously deposited layer of dielectric on a wafer face. Thereafter, trenches defining the horizontal copper routing are etched into the dielectric surface to a specified depth. The depth does not extend the whole way through the dielectric to underlying conductive features in a lower level metal layer or in the silicon substrate.
After the trenches have been etched, the photoresist is removed and a new etch resistant photoresist is deposited. This new layer of photoresist defines a via pattern in the dielectric of the wafer face. The vias are subsequently etched through the dielectric to the underlying metal lines or circuit elements. The vias provide a pathway between conductive features on different layers of the integrated circuit. After etching the vias, the photoresist is removed.
At this point, trenches and vias have been etched into the dielectric, but no conductive lines or interconnects have been added. In most implementations of the Damascene process, copper lines and interconnects are formed primarily by electrodeposition. But electrodeposition cannot commence unless there is an electrically conductive surface that can serve as a cathode onto which copper can deposit. Obviously, the electrically insulating dielectric layer is an inadequate cathode. To allow electrodeposition, a conductive surface must be provided over the surface of the dielectric layer and within the trenches and vias.
In addition, a diffusion barrier must be provided on the surface of the dielectric to prevent copper from diffusing into the dielectric surface. If copper were to diffuse into dielectric material, the dielectric layer's insulating properties would be compromised and the integrated circuit could fail.
With these goals in mind, the Damascene process typically employs physical vapor deposition (PVD) of first a diffusion barrier layer and then a copper seed layer. These layers, are deposited in succession into vias and routing lines, pre-etched in dielectric surfaces. Many suitable barrier layers may be employed such as tantalum, titanium nitride, etc. The copper seed layer serves as a conductive substrate unto which bulk copper may be electrodeposited. The seed layer is a thin layer (typically 800-2000 angstroms nominal) that covers the entire face of the wafer, following the sharp contours of the recessed features.
With the barrier and seed layers in place, the electroplating operation can begin. Electroplating fills the etched vias and trenches with copper and continues until the copper forms a continuous sheet over the entire wafer surface. Thereafter, the top portion of the copper is removed from the wafer face to expose the unetched regions of the dielectric layer and leave copper-filled interconnect circuitry.
One limitation of this process sequence is the difficulty in achieving a continuous PVD copper seed layer within high aspect ratio features without causing the features to close off at the top. Understand that as greater and greater quantities of copper seed are deposited by PVD, more complete coverage within a deep feature is attained. But this comes at the expense of pinch-off at the top of the feature, as depicted in FIG.
1
. As shown, pinch-off prematurely closes the upper portion (neck) of the trench or via, thereby preventing complete fill of the bottom portions of the feature.
The physics of the PVD process inherently deposits copper on the top or higher regions of a trench or via, thereby creating a narrow neck. This excess of copper at this neck of a recessed feature causes further build up during the subsequent electrodeposition process. Ultimately, the pinch-off region in the initial seed layer blocks further deposition in the lower regions of the feature and leaves a center void within the copper fill of the feature. It is now understood that pinch-off commonly occurs and when it does, it renders void-free filling by electrodeposition nearly impossible. This problem is particularly acute in high aspect ratio features of small width (e.g., AR greater than about 6:1 and width less than about 0.2 microns). Even smaller features of future device generations will require somewhat thinner PVD seeds in order to avoid pinch-off prior to or during electroplating.
But thinner seeds typically decrease PVD coverage within openings (recesses), leading to seed layer discontinuities near the base of the trench or via, and thus increasing bottom void formation.
FIG. 2
shows a discontinuous seed layer that can result from insufficient copper PVD. When the seed layer is discontinuous near the feature base, the copper growth during electrodeposition is slow or negligible in these areas. As a result, large voids can appear in the base of poorly seeded features because the electrodeposition process takes place only in areas of thicker seed layer (e.g., above the base of a via or trench).
Various options intended to provide seed layers suitable for extended Damascene fill by electrodeposition have been described. These include PVD/CVD Cu bilayers, all CVD seed, barrier optimization to improve PVD Cu smoothness at low thickness, atomic layer deposition, wet process seed deposition (Y. Lantasov, R. Palmans, K. Maex, Advanced Metallization Conf. Proc, pp 30-31, Oct. 3-5, 2000), and augmentation of PVD seed using wet processes (L. Chen, T. Ritzdorf, Semicon. Fabtech, July 2000). None of these is entirely suitable.
At least three patents mention that a seed layer may comprise two or more sub-layers, each serving a different role. These patents are U.S. Pat. No. 6,179,181B1 issued to Chen, U.S. Pat. No. 6,136,707 issued to Cohen, and U.S. Pat. No. 5,913,147 issued to Dubin et al. The latter two patents indicate that one process may involve initially depositing a partial seed layer by PVD, followed by depositing the remainder of the seed layer by electroless plating. However, each of these patents is essentially prophetic and contains no meaningful indication of how the electroless deposition may take place in such two-phase process.
The inventor's work has shown that new options for copper seed layers of future generation Damascene features, particularly high aspect ratio features, must be developed. Such processes should form a continuous layer of copper seed that does not cause pinch-off at the top of a high-aspect ratio feature.
SUMMARY OF THE INVENTION
The present invention addresses this need by providing a procedure and associated conditions for deposition of a thin and relatively continuous electroless copper film within sub-micron integrated circuit recessed features. The electroless copper film is deposited onto a partially completed seed layer, which may be discontinuous. In many instances, the partially completed seed layer is a previously deposited PVD copper film. For example, the film may be a PVD seed layer having a nominal thickness as at least about 250 angstroms. The electroless plating process may proceed until the electroless plated copper layer attains a thickness of between about 50-500 angstroms.
The continuous film formed by electroless deposition allows for subsequent filling of the sub-micron integrated circuit features by electrodeposition. Preferably, the electroless bath employed to form the continuous electroless copper film is composed of a reducing a
Andryuschenko Tatyana N.
Mayer Steven T.
Reid Jonathan D.
Webb Eric G.
Beyer Weaver & Thomas LLP
Novellus Systems Inc.
Pert Evan
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