Electrodepositing a metal in integrated circuit applications

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S674000, C438S675000, C438S677000, C438S678000, C257SE21495, C257SE21476

Reexamination Certificate

active

07902062

ABSTRACT:
A method is described in which a contact hole (18) to an interconnect (14) in an insulating layer (16) is fabricated. A barrier layer (20) is subsequently applied. Afterward, a photoresist layer (30) is applied, irradiated and developed. With the aid of a galvanic method, a copper contact (32) is then produced in the contact hole (18). Either the barrier layer (20) or an additional boundary electrode layer (22) serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.

REFERENCES:
patent: 3625758 (1971-12-01), Stahl et al.
patent: 5061985 (1991-10-01), Meguro et al.
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5242861 (1993-09-01), Inaba
patent: 5587337 (1996-12-01), Idaka et al.
patent: 5824599 (1998-10-01), Schacham-Diamand et al.
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5933758 (1999-08-01), Jain
patent: 6020266 (2000-02-01), Hussein et al.
patent: 6045892 (2000-04-01), Lee et al.
patent: 6054172 (2000-04-01), Robinson et al.
patent: 6080656 (2000-06-01), Shih et al.
patent: 6153521 (2000-11-01), Cheung et al.
patent: 6249055 (2001-06-01), Dubin
patent: 6297557 (2001-10-01), Bothra
patent: 6313529 (2001-11-01), Yoshihara et al.
patent: 6341006 (2002-01-01), Murayama et al.
patent: 6376374 (2002-04-01), Stevens
patent: 6413864 (2002-07-01), Pyo
patent: 6565729 (2003-05-01), Chen et al.
patent: 6756295 (2004-06-01), Lin et al.
patent: 6936906 (2005-08-01), Chung et al.
patent: 2002/0153569 (2002-10-01), Katayama
patent: 2003/0052013 (2003-03-01), Ando et al.
patent: 2000-150647 (2000-05-01), None
patent: 2002-124567 (2002-04-01), None
patent: 2002-520856 (2002-07-01), None
patent: WO 99/47731 (1999-09-01), None
patent: WO 02/47139 (2002-06-01), None
C.H. Seah et al., “Quality of Electroplated Copper Films Produced Using Different Acid Electrolytes”, J. Vac. Sci. Technol. B 17(5), Sep./Oct. 1999, pp. 2352-2356.
J.C. Hu et al., “Investigation on Multilayered Chemical Vapor Deposited Ti/TiN Films As the Diffusion Barriers in Cu and Al Metallization”, J. Vac. Sci. Technol. A 17(4), Jul./Aug. 1999, pp. 2389-2393.
Valery M. Dubin et al., “Selective and Blanket Electroless Copper Deposition for Ultralarge Scale Integration”, J. Electrochem. Soc., Vo. 144, No. 3, Mar. 1997, pp. 898-908.
D. Widmann, H. Mader, H. Fredrich, “Technologie hochintegrierter Schaltungen,” Mit 208 Abbildungen and 29 Tabellen, Springer.
Japanese Office Action dated Mar. 19, 2008, Japanese Patent Application No. 2004-554209, pp. 1-9.
European Search Report Dated Jan. 5, 2009 and English Translation of Same.
European Office Action Dated Jul. 3, 2009 and English Translation.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electrodepositing a metal in integrated circuit applications does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrodepositing a metal in integrated circuit applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrodepositing a metal in integrated circuit applications will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2670542

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.