Electrode wiring board subjected to counter measure against...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S355000, C257S072000, C349S040000

Reexamination Certificate

active

06380591

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an electrode wiring board having at least two electrode wiring layers formed to sandwich an insulating layer, and a display device using the same.
In recent years, as a display device using a liquid crystal, a display device or a liquid-crystal display (LCD) device which aims at a television display, a graphic display, and the like and has a large capacity and a high integration density is energetically developed and practically used. Not only a simple matrix type liquid-crystal display device which drives a liquid crystal by simply applying a voltage across a display electrode, i.e., a counter electrode and a display pixel electrode in a time sharing manner, but also a so-called an active matrix type in which a switching element is incorporated in each pixel to obtain a high-quality image has been developed in recent years and has been practically used.
In order to advance the spread of the active matrix type liquid-crystal display device, the price must be lowered by increasing a manufacturing yield.
Although there are several means for increasing the manufacturing yield, as one of them, a means for reducing a rate of generation of visible defects by electrostatic breakdown damage in the manufacturing steps can be brought. Conventional various measures are taken against the electrostatic breakdown damage.
In an active matrix type liquid-crystal display device subjected to the conventional counter measure against static electricity and using a thin film transistor as a switching element, the following method is known. That is, a ring-like conductive pattern called a short ring is arranged around a display cell formation region, so that all scanning lines, storage capacitance lines, and signal lines are rendered conductive.
FIG. 15
is a plan view showing the outline of a conventional TFT array substrate in a state wherein a short ring is formed during a manufacturing step. Referring to
FIG. 15
, a plurality of scanning lines
11
and storage capacitance lines
12
are formed in a same layer on a glass substrate
10
such that each storage capacitance line
12
is arranged between the scanning lines
11
to be parallel to the scanning lines
11
.
Pixel electrodes
13
arranged in a matrix are formed over the storage capacitance line
12
through an insulating film. After another insulating film is formed on the entire surface of the resultant structure, a plurality of signal lines
14
are formed in a direction traversing each the scanning line
11
and the storage capacitance line
12
.
Scanning line test electrodes
15
, feeding electrodes
16
, and storage capacitance line test electrodes
17
are formed outside a pixel electrode formation region.
The scanning lines
11
, the storage capacitance lines
12
, and the signal lines
14
are electrically connected to each other on a stage in the manufacturing steps by a short ring
18
formed around a display cell formation region. The connection portions among the short ring
18
, the scanning lines
11
, the storage capacitance lines
12
, and the signal lines
14
are cut off on the final stage of the manufacturing steps.
In this manner, when all the scanning lines
11
, the storage capacitance lines
12
, and the signal lines
14
are rendered conductive by the short ring
18
, a TFT array substrate of the active matrix type liquid-crystal display device prevents a potential difference from being generated between the lines even if static electricity is charged after formation of the short ring. For this reason, electrostatic breakdown damage does not occur.
However, in fact, static electricity is frequently charged in the step before the step of forming the short ring. In this case, since a large potential difference is generated between lines, the electrostatic breakdown damage occurs in a wiring structure or an insulating film formed before the step of forming a short ring on the TFT array substrate.
For example, in the step before the step of forming the short ring
18
shown in
FIG. 15
, the scanning lines
11
, the storage capacitance lines
12
, and the test electrodes
15
and
17
connected to these lines are formed. Thereafter, a resist for performing a photoetching operation for forming another pattern is coated on the substrate
10
, and heating is performed on the planar stage for evaporating the solvent of the resist.
After the heating step, as shown in
FIG. 16
, the TFT array substrate
10
is moved on a conveyer belt
22
while being floated by a plurality of conveyer rollers
21
from the conveyer belt
22
to be conveyed to the next step. When the TFT array substrate
10
is conveyed while being floated by the plurality of convey rollers
21
, static electricity of, e.g., several thousands volts is charged between the TFT array substrate
10
and the conveyer belt
22
by peeling charge.
In this case, as shown in
FIG. 16
, the conveying position of the TFT array substrate
10
is corrected by metal arms
23
connected to the conveyer belt
22
. At this time, charges accumulated in the TFT array substrate
10
rapidly move toward the metal arm
23
by the contact between the metal arm
23
and the TFT array substrate
10
, so that electrostatic breakdown damage occurs in the wiring structure or insulating film of the TFT array substrate
10
.
More specifically, as shown in
FIG. 17
, in a state wherein a region
24
serving as a part of the TFT array substrate
10
is charged by negative static electricity of several thousands volts, when the grounded metal arm
23
is brought into contact with the region
24
, the negative charges rapidly move from the region
24
of the TFT array substrate
10
to the metal arm
23
to cause discharging to occur.
At this time, electrostatic charges on a scanning line
11
a
or a storage capacitance line
12
a
arranged at a position near the charge region
24
of the TFT array substrate
10
transmits a scanning line
11
b
arranged between the scanning line
11
a
or the storage capacitance line
12
a
and the metal arm
23
rapidly, so that the charges rapidly move in an insulating film such as an insulating interlayer or a thin film semiconductor layer
26
in a discharging state.
Here, in
FIG. 17
, the position of a signal line
14
a
to be formed in the subsequent; step is indicated by a two-dash line. Therefore, when such discharging occurs after the signal line
14
a
is formed, charges may flow from the scanning line
11
a
or the storage capacitance line
12
a
to the metal arm
23
through the signal line
14
a
. As a result, the insulating states between the scanning line
11
a
and the signal line
14
a
and between the storage capacitance line
12
a
and the signal line
14
a
are broken.
As the result of the discharging, as shown in
FIG. 18
, discharging occurs between the scanning line
11
a
and the metal arm
23
shown in
FIG. 17
, and a pinhole-like or crack-like damaged portion
27
is formed by the electrostatic breakdown along the discharging, in the insulting film
25
and thin film semiconductor layer
26
formed on the scanning line
11
a
. When the signal line
14
a
is formed on the damaged portion
27
in the subsequent step, as shown in
FIG. 19
, the signal line
14
a
and the scanning line
11
a
are short-circuited to each other through the damaged portion
27
. For this reason, a visible defect such as a line defect occurs in a pixel array during a display operation upon completion of the display device.
There is provided an active matrix type liquid-crystal display device which is subjected to a counter measure against electrostatic breakdown damage by forming discharging projections in an electrode wiring layer adjacent to each other without using a short ring.
For example, as disclosed in U.S. Pat. No. 5,677,745, a display device having the following arrangement is known. That is, a TFT is used as a switching element, and a signal line is constituted by a laminated structure including at least a semiconductor layer and a metal layer. The outer shapes of the respective la

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