Electrode structure for transistors, non-volatile memories...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S295000, C257S303000, C257S336000, C257S340000, C257S344000, C257S408000, C257S524000, C257S547000, C257S900000

Reexamination Certificate

active

06262451

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to novel contact electrode and gate structures and more specifically to very small dimension contact electrode and gate structures for the fabrication of novel semiconductor devices.
BACKGROUND OF THE INVENTION
In the semiconductor industry, devices are becoming smaller and components, e.g. control electrodes, contact electrodes, gates, etc., within the devices are so small they are very difficult to fabricate. Side wall spacers have found some limited use in various manufacturing processes. The most typical application of side wall spacers is to space heavily doped regions away from the gate electrode of a transistor via the so called “self-aligned” implant process. In this process a gate is formed and side wall spacers are formed on the sides of the gate. The source and drain are then implanted using the gate and side wall spacers as an implant mask. The heavily doped source and drain regions are spaced from the gate by the width of the side wall spacers, which is determined by the thickness of the side wall spacer material deposited before directional etching. The device breakdown voltage is thus improved.
It would be highly desirable to utilize side wall spacers in the fabrication of additional semiconductor devices.
It is a purpose of the present invention to provide a new and improved electrode structure for semiconductor devices.
It is another purpose of the present invention to provide a new and improved electrode structure for new and improved semiconductor devices.
It is a further purpose of the present invention to provide a new and improved electrode structure for semiconductor devices which is easy to fabricate and which is useful in the fabrication of multiple threshold voltage transistors, memory devices, etc.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in an electrode structure, e.g. a source, drain, or gate, for semiconductor devices fabricated in accordance with the present invention. In a typical example of the fabrication of an electrode structure, first electrode material is positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on the first side wall and defines a second side wall parallel to and spaced from the first side wall. Second electrode material is formed in overlying relationship to the substrate and on the second side wall so as to define a third side wall parallel to and spaced from the second side wall. The first and second electrode materials are connected as first and second electrodes in a common semiconductor device. Additional electrodes can be formed by forming electrode material on additional side walls.
In another embodiment, the first and second electrode materials are formed on a gate dielectric, which is formed on the surface of the substrate. The gate dielectric for the first and second gates may be the same material and thickness or it may be different material and/or different thicknesses to form a multiple threshold transistor.
The novel electrode structure may be utilized to form novel memory devices. Also, as will be understood by those skilled in the art, the electrode fabrication steps can be used to form various electrodes, such as sources, drains, gates, etc., and the gate description utilized herein is only for purposes of illustration and example.


REFERENCES:
patent: 5108939 (1992-04-01), Manley et al.
patent: 5413948 (1995-05-01), Pfiester et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5543643 (1996-08-01), Kapoor
patent: 5599726 (1997-02-01), Pan
patent: 5663586 (1997-09-01), Lin
patent: 5760435 (1998-06-01), Pan
patent: 5825609 (1998-10-01), Andricacos et al.
patent: 0329047 (1989-02-01), None
patent: 0335395 (1989-03-01), None

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