Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-20
2003-02-25
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S317000
Reexamination Certificate
active
06525367
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-266152 filed on Sep. 20, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, and more particularly, to a semiconductor devices such as nonvolatile memory or MOS transistor in which its tunneling oxide film is an oxy-nitride film and at least a part of its control gate is a silicide film or a metal film with a high melting point, and its manufacturing method, which are applicable to NAND EEPROM (electrically erasable and programmable read-only memory), for example.
2. Related Background Art
FIG. 1
is a plan view that shows general configuration of a cell array in a NAND flash memory, and
FIG. 2
is a circuit diagram of the cell array of the NAND flash memory shown in FIG.
1
.
The cell array of the NAND flash memory shown in
FIGS. 1 and 2
is composed of cell transistors CT
1
, CT
2
, . . . , CTn in which a plurality of n-channel MOS transistors each having a floating gate and a control gate are connected in series; a selection transistor ST
1
in form of an n-channel MOS transistor connected between the drain at one end of the serially connected cell transistors CT
1
, CT
2
, . . . , CTn and a bit line BL; a selection transistor ST
2
in form of an n-channel MOS transistor connected between the source at the other end of the serially connected cell transistors CT
1
, CT
2
, . . . , CTn and a source line GND; selection lines SL
1
and SL
2
connected to control gates SG
1
and SG
2
of the selection transistors ST
1
and ST
2
, respectively; and word lines WL
1
, WL
2
, . . . , WLn connected to control gates CG
1
, CG
2
, . . . , CGn of the cell transistors CT
1
, CT
2
, . . . , CTn. The transistors are made in a common well of a common substrate, and the selection line SL
1
, word lines WL
1
, WL
2
, . . . , WLn and selection line SL
2
are arranged in sequence substantially in parallel in the direction of rows. The other ends of the word lines WL
1
, WL
2
, . . . , WLn are connected to a connection pad for connection to a peripheral circuit via aluminum wirings.
Explained below is a structure of a cell array of a conventional NAND flash memory and its manufacturing method with reference to a cross-sectional view of a portion corresponding to the B-B′ line of FIG.
1
.
FIG. 3
is the cross-sectional view that shows the structure of the cell array in the conventional NAND flash memory.
The cell array of the conventional NAND flash memory shown in
FIG. 3
is composed of a silicon substrate
1
; a first gate insulating film
3
in form of an oxy-nitride film stacked on the top surface of the silicon substrate
1
; floating gates
4
in form of a polycrystalline silicon film stacked on predetermined locations of the first gate insulating film
3
; a second gate insulating film
5
in form of a silicon oxide film stacked on the floating gates
4
; control gates made of a polycrystalline silicon film
6
and a tungsten silicide film
7
sequentially stacked on the second gate insulating film
5
; an oxide film
8
stacked on the tungsten silicide film
7
; a secondary oxide film
11
in form of a silicon oxide film stacked on side surfaces of the oxide film
8
, the tungsten silicide film
7
, and the polycrystalline silicon film
6
, the second gate insulating film
5
, the polycrystalline silicon film
4
and top surface of the oxide film
8
; and diffusion layers
12
formed in predetermined regions of the top surface portion of the silicon substrate
1
.
The cell array of the above conventional NAND flash memory is made by the following manufacturing method.
FIGS. 4A through 4G
are cross-sectional views of the cell array of the conventional NAND flash memory shown in
FIG. 3
under a process of its manufacturing method.
First as shown in
FIG. 4A
, the silicon oxide film
2
, 7 nm thick, is made on the silicon substrate
1
by thermal oxidation.
After the silicon oxide film
2
is formed, as shown in FIG.
4
B, the silicon oxide film
2
is nitrified by using ammonium gas (NH
3
) and next oxidized to form an oxy-nitride film
3
. This oxy-nitride film
3
serves as a first gate oxide film, and it is normally called a tunneling oxide film.
After the oxy-nitride film
3
is made, as shown in
FIG. 4C
, the polycrystalline silicon film
4
, 200 nm thick and doped with phosphorus as an impurity, is formed on the oxy-nitride film
3
by LPCVD. The polycrystalline silicon film
4
is later processed to a first gate electrode, and it is normally called a floating gate. After the polycrystalline silicon film
4
is made, the second gate insulating film
5
, 120 nm thick, is stacked on the polycrystalline silicon film
4
by LPCVD. After the second gate insulating film
5
is formed, the polycrystalline silicon film
6
doped with phosphorus as an impurity is stacked on the second gate insulating film
5
by LPCVD, and the tungsten silicide film
7
, which is a low-resistance wiring material, is further stacked on the polycrystalline silicon film
6
by CVD. The polycrystalline silicon film
6
and the tungsten silicide film
7
, altogether, form the second gate electrode which is normally called a control gate. After the tungsten silicide film
7
is formed, the oxide film
8
is made on the tungsten silicide film
7
.
After the oxide film
8
is made, as shown in
FIG. 4D
, a photo resist
9
is spread on the oxide film
8
and processed into a predetermined pattern by photo-etching. Then, using the photo resist
9
as a mask, the oxide film
8
is processed into the same pattern by RIE or other dry etching. After the oxide film
8
is formed, the photo resist
9
is removed.
After removal of the photo resist
9
, as shown in
FIG. 4E
, using the oxide film
8
as a mask, the tungsten silicide film
7
, the polycrystalline silicon film
6
, the second gate insulating film
5
and the polycrystalline silicon film
4
are selectively removed sequentially in the vertical direction by anisotropic etching using RIE or other dry etching technique.
After that, for the purpose of preventing leak current at the gate end, improving surface resistance to voltage of the peripheral circuit MOS transistor, i.e. resistance to voltage of the gate insulating film and recovering damages introduced into the gate oxide film through the gate electrode by RIE, and for other purposes, the silicon oxide film
11
is stacked on side surfaces of the oxide film
8
, the tungsten silicide film
7
, the polycrystalline silicon film
6
, the second gate insulting film
5
and the polycrystalline silicon film
4
and the top surface of the oxide film
8
as shown in FIG.
4
F. Normally, this oxidation process is called secondary oxidation process, and the oxide film
11
made in this step is called secondary oxide film.
After the secondary oxide film
11
is made, as shown in
FIG. 4G
, for the purpose of making source regions and drain regions, an impurity is ion-implanted into the silicon substrate
1
and activated by annealing to create diffusion layers
12
and make memory transistors. As a result, the structure of the cell array of the conventional NAND flash memory shown in
FIG. 3
is obtained.
However, in the case where an oxy-nitride film is used as the tunneling oxide film
3
like the cell array of the conventional NAND flash memory as discussed above, nitrogen concentration of the tunneling oxide film
3
is high, and especially after RIE for gate processing, nitrogen concentration of the tunneling oxide film
3
becomes high along the circumferential portion of the bottom of the floating gate
4
. As a result, as shown in
FIGS. 4F and 4G
, it becomes difficult to make the secondary oxide film
11
along the circumference portion of the bottom of the floating gate
4
, and it invites deterioration of the device property, decrease of the reli
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Minh Loan
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