Electro-static discharge protection of CMOS integrated circuits

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257355, 257786, 361220, H01L 2360, H01L 2362

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active

060435399

ABSTRACT:
In a semiconductor integrated circuit, I/O buffer circuits that include ESD protection are generally provided for each I/O pad. According to the invention, unused pads, i.e. pads that are not connected to core circuitry according to an initial design, are connected to other pads that are used for connection to the core circuitry, thereby employing the unused pads to improve ESD protection of susceptible pads. This approach has the advantages of greater ESD protection without increasing silicon area and without adding any additional steps to the usual fabrication process. The inventive concept is especially useful for augmenting ESD protection of corner pads without requiring new or custom ESD protection circuits. This invention can be easily implemented into known layout tools.

REFERENCES:
patent: 5410254 (1995-04-01), Consiglio
patent: 5712753 (1998-01-01), Yeh et al.
patent: 5715127 (1998-02-01), Yu
patent: 5818086 (1998-10-01), Lin et al.
Matsumoto, et al., "New Failure Mechanism due to Non-Wired Pin ESD Stressing," EOS/ESD Symposium, 1994, pp. 2.5.1-2.5.6.

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